Freescale Semiconductor MPC5553 Manuals

Manuals and User Guides for Freescale Semiconductor MPC5553. We have 1 Freescale Semiconductor MPC5553 manual available for free PDF download: Reference Manual

Freescale Semiconductor MPC5553 Reference Manual

Freescale Semiconductor MPC5553 Reference Manual (1208 pages)

Brand: Freescale Semiconductor | Category: Microcontrollers | Size: 7 MB

Table of Contents

Overview

6
- Errata for Revision 5
  3
- Table of Contents
  6
- MPC5553/MPC5554 Microcontroller Reference Manual
  21
  - Introduction
    22
  - Features
    26
- MPC5553-Specific Modules
  32
- MPC5500 Family Comparison
  33
- Detailed Features
  34
- Chapter 1
  
  35
  - System Bus Crossbar Switch
    35
  - Edma
    36
  - Ecsm
    37
  - Sram
    38
- Chapter 19
  
  39
  - Eqadc
    39
  - Flexcan
    40
  - Calibration Bus (MPC5553 Only)
    41
  - Multi-Master Operation Memory Map
    44
    
    Revision History
    46
    
    Block Diagram
    48
    
    External Signal Description
    51
- Chapter 2
  
  52
  - MPC5553 Signals Summary
    52
  - MPC5554 Signals Summary
    69
  - Detailed Signal Description
    83
  - External Bus Interface (EBI) Signals
    84
  - External Data Signals
    85
  - Nexus Signals
    90
  - JTAG Signals
    91
  - Flexcan Signals
    92
  - Esci Signals
    93
  - Eqadc Signals
    96
  - Etpu Signals
    99
  - Emios Signals
    101
  - Clock Synthesizer Signals
    102
  - I/O Power/Ground Segmentation
    104
  - Etpu Pin Connections and Serialization
    108
    
    Etpua[16:31]
    110
  - Emios Pin Connections and Serialization
    113
    
    Revision History
    114
    
    Introduction
    116
    
    Block Diagram
    117
    
    Features
    118
- Chapter 3 Microarchitecture Summary
  
  120
  - Core Registers and Programmer's Model
    121
    
    Power Architecture Registers
    123
    
    Core-Specific Registers
    125
    
    E200Z6 Core Complex Features Not Supported in the MPC5553/MPC5554
    126
    
    Functional Description
    128
    
    L1 Cache
    135
    
    Interrupt Types
    139
- Chapter 17
  
  140
  - Bus Interface Unit (BIU)
    140
  - Timer Facilities
    141
  - SPE Programming Model
    142
    
    Revision History
    143
    
    Introduction
    144
    
    External Signal Description
    145
  - Boot Configuration (BOOTCFG[0:1])
    146
  - Functional Description
    150
  - Reset Configuration and Configuration Pins
    153
  - Reset Configuration Timing
    158
  - Reset Flow
    160
    
    Revision History
    162
    
    Introduction
    164
    
    Features
    166
5.2 External Signal Description

167
- Base + 0X0004- Base + 0X001F
  167
- Base + 0X0020
  167
- Base + 0X0024
  167
- Base + 0X003F
  167
- Base + 0X0040
  167
- Base + 0X0044
  167
- Base + 0X0048
  167
- Base + 0X004C
  167
- Base + 0X0053
  167
  - External Signal Description
    167
  - Register Descriptions
    168
  - Pbridge_A_Pacr0
    173
- Pbridge_A_Opacr0
  173
- Pbridge_A_Opacr1
  173
- Pbridge_A_Opacr2
  174
  - Pbridge_B_Pacr0
    174
  - Pbridge_B_Pacr2
    174
- Pbridge_B_Opacr0
  174
- Pbridge_B_Opacr1
  174
- Pbridge_B_Opacr2
  174
- Pbridge_B_Opacr3
  174
- Functional Description
  175
- Chapter 7
  
  176
  - General Operation
    176
    
    Revision History
    178
    
    Introduction
    180
    
    Block Diagram
    181
    
    Features
    182
    
    External Signal Description
    183
    
    Memory Map/Register Definition
    186
    
    Register Descriptions
    187
    
    Functional Description
    284
  - Reset Control
    285
  - GPIO Operation
    286
    
    Revision History
    291
    
    Introduction
    292
    
    Overview
    293
    
    Modes of Operation
    294
    
    Register Descriptions
    295
    
    Functional Description
    299
  - Master Ports
    300
  - Priority Assignment
    301
    
    Revision History
    303
    
    Introduction
    304
    
    Memory Map/Register Definition
    305
8.2.1 Register Descriptions

306
- Register Descriptions
  306
- ECC Configuration Register (ECSM_ECR)
  307
- ECC Status Register (ECSM_ESR)
  307
- Flash ECC Address Register (ECSM_FEAR)
  310
- Flash ECC Attributes Register (ECSM_FEAT)
  311
- Flash ECC Master Number Register (ECSM_FEMR)
  311
- RAM ECC Address Register (ECSM_REAR)
  314
- RAM ECC Attributes Register (ECSM_REAT)
  315
- RAM ECC Master Number Register (ECSM_REMR)
  315
  - Initialization/Application Information
    318
  - Revision History
    319
  - Introduction
    320
  - Block Diagram
    321
  - Modes of Operation
    322
  - Memory Map/Register Definition
    323
  - Register Descriptions
    327
  - Functional Description
    349
- Edma Basic Data Flow
  351
- Edma Performance
  353
- Initialization / Application Information
  356
- DMA Programming Errors
  358
- DMA Request Assignments
  359
Table of Contents

360
- DMA Arbitration Mode Considerations
  361
- DMA Transfer
  363
- TCD Status
  366
- Channel Linking
  367
- Dynamic Programming
  368
  - Revision History
    369
  - Introduction
    370
  - Block Diagram
    371
  - Features
    374
  - External Signal Description
    376
  - Memory Map/Register Definition
    377
  - Register Descriptions
    379
  - Functional Description
    385
- Emios_Gfr_F1
  387
- Emios_Gfr_F10
  387
- Emios_Gfr_F11
  387
- Emios_Gfr_F2
  387
- Emios_Gfr_F3
  387
- Emios_Gfr_F4
  387
- Emios_Gfr_F6
  387
- Emios_Gfr_F7
  387
- Emios_Gfr_F8
  387
- Emios_Gfr_F9
  387
- Emios Channel 1 Flag
  393
- Emios Channel 2 Flag
  393
- Emios Channel 3 Flag
  393
- Emios Channel 4 Flag
  393
- Emios Channel 8 Flag
  393
- Emios.gfr[F1]
  393
- Emios_Gfr_F16
  393
- Emios_Gfr_F17
  393
- Emios_Gfr_F18
  393
- Emios_Gfr_F19
  393
- Emios Channel 7 Flag
  394
- Chapter 10
  
  398
  - Priority Management
    398
    
    Details on Handshaking with Processor
    400
    
    Initialization/Application Information
    402
    
    ISR, RTOS, and Task Hierarchy
    404
    
    Order of Execution
    405
    
    Priority Ceiling Protocol
    406
    
    Selecting Priorities According to Request Rates and Deadlines
    409
    
    Lowering Priority Within an ISR
    410
    
    Examining LIFO Contents
    411
    
    Revision History
    412
    
    Introduction
    416
    
    Overview
    423
- Chapter 11
  
  424
  - FMPLL Modes of Operation
    424
    
    External Signal Description
    427
    
    Functional Description
    435
  - Clock Operation
    437
  - Clock Configuration
    440
    
    Revision History
    448
    
    Introduction
    450
    
    Block Diagram
    451
    
    Overview
    452
    
    Modes of Operation
    453
    
    External Signal Description
    455
    
    Detailed Signal Descriptions
    456
- Chapter 12
  
  460
  - Signal Function/Direction by Mode
    460
    
    Memory Map/Register Definition
    462
    
    Functional Description
    469
  - External Bus Operations
    475
  - Initialization/Application Information
    517
  - Connecting an MCU to Multiple Memories
    520
  - Summary of Differences from Mpc5Xx
    521
    
    Revision History
    523
    
    Introduction
    524
    
    Features
    526
    
    External Signal Description
    527
  - Flash Memory Map
    529
    
    Register Descriptions
    531
    
    Functional Description
    546
  - Flash Memory Array: User Mode
    548
  - Flash Memory Array: Stop Mode
    559
    
    Revision History
    560
    
    Introduction
    562
    
    Block Diagram
    563
    
    Overview
    564
    
    Features
    565
  - Address Recognition Options
    566
- Chapter 14
  
  566
  - Detailed Memory Map (Control/Status Registers)
    567
  - MIB Block Counters Memory Map
    568
  - Registers
    571
  - Functional Description
    595
  - User Initialization (Prior to Asserting ECR[ETHER_EN])
    596
  - Microcontroller Initialization
    597
  - FEC Frame Transmission
    598
  - FEC Frame Reception
    599
  - Ethernet Address Recognition
    600
  - Hash Algorithm
    602
  - Full-Duplex Flow Control
    605
  - Inter-Packet Gap (IPG) Time
    606
  - Buffer Descriptors
    608
    
    Ethernet Receive Buffer Descriptor (Rxbd)
    610
    
    Ethernet Transmit Buffer Descriptor (Txbd)
    612
    
    Revision History
    613
    
    Introduction
    616
  - External Signal Description
    617
- Chapter 15
  
  618
  - Access Timing
    618
  - Reset Operation
    619
  - Initialization/Application Information
    620
- Chapter 16
  
  621
  - Revision History
    621
  - Introduction
    624
    
    Modes of Operation
    625
    
    Functional Description
    626
    
    Interrupts
    638
    
    Introduction
    640
    
    Block Diagram
    641
    
    Overview
    642
    
    External Signal Description
    644
    
    Memory Map/Register Definition
    646
    
    Register Description
    647
    
    Functional Description
    661
    
    Global Clock Prescaler Submodule (GCP)
    663
  - Initialization / Application Information
    704
    
    Revision History
    706
    
    Introduction
    708
- Chapter 13
  
  709
  - Block Diagram
    709
- Chapter 18
  
  710
  - Etpu Operation Overview
    710
  - Features
    715
  - Modes of Operation
    717
  - Detailed Signal Description
    718
- Chapter 5
  
  721
- Chapter 6
  
  721
  - Memory Map/Register Definition
    721
    
    Register Description
    722
    
    Functional Description
    752
    
    Initialization/Application Information
    753
    
    Introduction
    756
    
    Overview
    757
    
    Features
    758
    
    Modes of Operation
    759
  - External Signals
    761
  - Memory Map/Register Definition
    764
    
    Eqadc Register Descriptions
    768
    
    On-Chip ADC Registers
    791
    
    Functional Description
    798
    
    Data Flow in the Eqadc
    799
    
    Command/Result Queues
    814
    
    Eqadc Command Fifos
    815
    
    Result Fifos
    836
    
    On-Chip ADC Configuration and Control
    839
    
    Internal/External Multiplexing
    847
    
    Eqadc Edma/Interrupt Request
    851
    
    Eqadc Synchronous Serial Interface (SSI) Submodule
    854
    
    Analog Submodule
    858
  - Initialization/Application Information
    860
    
    Eqadc/Edma Controller Interface
    864
    
    Sending Immediate Command Setup Example
    865
    
    Modifying Queues
    866
    
    ADC Result Calibration
    867
    
    Eqadc Versus QADC
    869
- Appendix C Revision History
  
  872
  - Introduction
    874
  - Block Diagram
    875
  - Features
    876
  - Chapter 24
    
    877
    
    Modes of Operation
    877
    
    External Signal Description
    878
    
    Memory Map/Register Definition
    879
    
    Register Descriptions
    881
    
    Functional Description
    905
  - Chapter 25 Modes of Operation
    
    906
    
    Start and Stop of DSPI Transfers
    907
    
    Serial Peripheral Interface (SPI) Configuration
    908
    
    Deserial Serial Interface (DSI) Configuration
    911
    
    Combined Serial Interface (CSI) Configuration
    923
    
    DSPI Baud Rate and Clock Delay Generation
    925
    
    Transfer Formats
    927
    
    Continuous Serial Communications Clock
    934
    
    Interrupts/Dma Requests
    935
    
    Power Saving Features
    937
    
    Baud Rate Settings
    938
    
    Delay Settings
    939
    
    Mpc5Xx QSPI Compatibility with the DSPI
    940
    
    Calculation of FIFO Pointer Addresses
    941
    
    Revision History
    942
    
    Introduction
    944
    
    Overview
    945
    
    External Signal Description
    946
    
    Register Definition
    947
    
    Functional Description
    962
    
    Baud Rate Generation
    963
    
    Transmitter
    964
    
    Receiver
    968
    
    Single-Wire Operation
    974
    
    Loop Operation
    975
    
    Interrupt Operation
    976
    
    Using the LIN Hardware
    979
    
    Revision History
    983
    
    Introduction
    986
    
    Block Diagram
    987
    
    Features
    988
    
    External Signal Description
    989
  - Chapter 23 Detailed Signal Description
    
    990
  - Chapter 22
    
    991
    
    Message Buffer Structure
    991
    
    Register Descriptions
    994
    
    Functional Description
    1009
    
    Receive Process
    1010
    
    Message Buffer Handling
    1011
    
    CAN Protocol Related Features
    1012
    
    Modes of Operation Details
    1015
    
    Interrupts
    1016
    
    Flexcan2 Addressing and RAM Size
    1017
    
    Revision History
    1018
    
    Introduction
    1020
    
    Detailed Signal Description
    1021
    
    Functional Description
    1022
    
    Initialization/Application Information
    1024
    
    Revision History
    1027
    
    Introduction
    1028
    
    Block Diagram
    1029
    
    Overview
    1030
    
    External Signal Description
    1031
    
    Register Definition
    1032
    
    Functional Description
    1034
    
    JTAGC Instructions
    1036
    
    Boundary Scan
    1038
    
    Revision History
    1039
    
    Introduction
    1040
    
    Block Diagram
    1041
    
    Modes of Operation
    1043
    
    External Signal Description
    1044
    
    Memory Map
    1045
    
    NDI Functional Description
    1049
    
    Configuring the NDI for Nexus Messaging
    1050
    
    Programmable MCKO Frequency
    1051
    
    System Clock Locked Indication
    1052
    
    Memory Map/Register Definition
    1053
    
    NPC Functional Description
    1056
    
    Auxiliary Output Port
    1057
    
    NPC Initialization/Application Information
    1063
    
    Nexus Dual Etpu Development Interface (NDEDI)
    1064
    
    E200Z6 Class 3 Nexus Module (NZ6C3)
    1065
  - Chapter 21
    
    1066
    
    Overview
    1066
    
    Enabling Nexus3 Operation
    1067
    
    NZ6C3 Memory Map/Register Definition
    1071
    
    Development Control Register 1, 2 (DC1, DC2)
    1072
    
    Development Status Register (DS)
    1075
    
    Read/Write Access Data (RWD)
    1077
    
    Watchpoint Trigger Register (WT)
    1078
    
    Data Trace Control Register (DTC)
    1079
    
    Data Trace Start Address Registers 1 and 2 (Dtsan)
    1080
    
    Data Trace End Address Registers 1 and 2 (Dtean)
    1081
    
    NZ6C3 Register Access Via JTAG / Once
    1082
    
    Ownership Trace
    1083
    
    Program Trace
    1084
    
    Data Trace
    1093
    
    Watchpoint Support
    1099
    
    NZ6C3 Read/Write Access to Memory-Mapped Resources
    1100
    
    Examples
    1105
    
    IEEE‚ 1149.1 (JTAG) RD/WR Sequences
    1108
    
    Nexus Crossbar Edma Interface (NXDM)
    1110
    
    External Signal Description
    1111
    
    NXDM Registers
    1112
    
    Functional Description
    1121
    
    Watchpoint Support
    1127
    
    Revision History
    1128
- Appendix A
  
  1130
  - A.1 Module Base Addresses
    1130
  - A.2 Detailed Register Map
    1131
  - B.1 Overview
    1196
  - B.2 Calibration Bus
    1198
  - B.3 Device Specific Information
    1199
- Appendix B
  
  1200
  - B.3.1 MPC5554 Calibration Bus Implementation
    1200
  - B.4.2 Pad Ring
    1201
  - B.4.3 Clkout
    1202
  - B.7 Revision History
    1203
  - C.1 Changes between Rev. 4 and Rev. 5
    1204

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