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FB<Vpin1 => Skip high
FB
100k
Skip
7
adjust
+
450mV
25r
FB>1.6*Vpin1 =>Stby_detect RESET
Fault
3
−
detect
+
2.5V
Vcc
10k
PFC_Vcc
1
pfcON
1mA
Vdd
6
SS / timer
2
REF5V
+
5V
BO_in
BO
5
+
0.5V / 0.25V
Vdd
Rt
4
OSC
2.5V
Vdd
20k
FB
8
to Skip
NCP1239
Skip
+
−
Stby_detect
S
Q
15r
Q
R
+
−
S
Fault
Q
Q
R
Vcc < 4V
pfcOFF
Stby
Startup Phase
Vdd
OVL
Stby_detect
Soft−Start
and timer
Error_Flag
management
Soft−Start
Jittering
Ipk limit
Modulation
Ramp
3.2V
Compensation
−
BO_out
+
Vstop
Oscillator
CLK
−
+
Jittering
Modulation
"Jittered"
Reference
/ 3
Soft−Start
Ipk limit
Figure 4. NCP1239V Internal Circuit Architecture
http://onsemi.com
UVLOs
Latch
Reset
Internal
Thermal
Shutdown
UVLO
TSD
(Vcc<VccOFF)
OVL
regOUT
Vdd
stdwn
Vstop
S
Q
Q
R
Divider by 2
Output
Buffer
OUTon
pfcON
32k
CLK
S
Q
Q
R
LEB
Skip
+
−
+
−
OSC
0.9V
Error flag
8
HV
16
15
14
Regul
13
Vcc
Vcc<7V
Drv
12
14V
clamp
11
GND
10
CS
Vdd
Idmax
Dmax
9
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