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300.0M
200.0M
100.0M
The skip−cycle takes place at low peak currents which guaranties noise free operation
PFC Inhibition in Standby
The circuit detects a light load condition by permanently
monitoring the skip−cycle comparator activity: in normal
load condition this comparator keeps quiet. As soon as the
load strongly decreases, this comparator starts to toggle at a
low frequency rate: we are entering skip−cycle and the
opto−coupler operates in a digital manner, ON/OFF.
Figure 56 shows the way skip−cycle is detected. In skip
mode, the feedback voltage oscillates around V
voltage is applied to the Pin 7, a 430 mV voltage source
supplies a default value through a high impedance resistor).
In these conditions, the skip comparator ("COMP1") that
turns on and off (to adjust the skip mode bunches of pulses),
sets the standby detection latch. A second comparator
("COMP2") compares the feedback voltage (FB or V
1.7*V
.
pin7
As long as the load keeps light, FB does not exceed
1.7*V
(i.e., 0.74 V typical if no voltage is forced to
pin7
Max peak
current
0
315.4U
882.7U
(If no
pin7
pin8
A delay is inserted to avoid false tripping of the GTS signal
http://onsemi.com
NCP1239
25% of max Ip
1.450M
2.017M
2.585M
Figure 56.
Pin 7). A timer counts down and if COMP2 keeps high for
100 ms (typically with 390 nF on Pin 6), the NCP1239
considers that the system runs in the standby mode. Pin 1
turns high, a 10 kW resistor tying the pin to V
in Figure 39, Pin 1 directly drives a pnp transistor that is
connected between V
off in standby. As a result, this transistor stops feeding the
PFC V
and ultimately shuts the PFC down.
CC
As soon as FB exceeds 1.7*V
standby mode without any delay by forcing a 1 mA sinking
current source on Pin 1, that re−activates the pnp transistor
and then the PFC stage.
One can note that there is a 1/3 ratio between the actual
current setpoint and the feedback value FB. Therefore the
) to
default thresholds for standby detection and normal mode
recovery (0.43 V, 0.74 V) actually corresponds to the
140 mV and 250 mV setpoints.
70%
Figure 57.
34
. If as shown
CC
and the PFC V
, this switch turns
CC
CC
, the circuit leaves the
pin7
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