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If by design we have selected a 47 mF V
becomes easy to evaluate the burst period and its duty−cycle.
This can be done by properly identifying all time events on
Figure 42 and applying the classical formula: t = C * DV / i.
To simplify, let's consider t1 starts while V
Then:
•
3 = 400 mA, DV= 11.2 – 6.9 = 3 V !
t1: I = I
CC
t1 = 505 ms
•
t2: I = 3.6 mA, DV= 16.4 – 6.9 = 9.5 V ! t2 = 124 ms
•
t3: I = 400 mA, DV= 16.4 – 11.2 = 5.2 V ! t3 = 611 ms
•
t'1 = t1= 505 ms
•
t'2 = t2 = 124 ms
The total period duration is thus the sum of all these events
which leads to Tfault = 1793 ms. If Tpulse = 100 ms, then
our burst duty−cycle equals 100/(1869 + 100) ≈ 5%, which
is excellent.
In fact, the calculation assumption, t1 starts while
V
= V
, gives the worse case since the duty cycle is
CC
CCOFF
calculated in the case where Tpulse exactly equals the active
phase duration (switching period when V
V
to V
).
CCON
CCOFF
V
CC
Drv
Pin 3
When Vpin3 exceeds 2.4 V, NCP1239 permanently latches−off the output pulses0until its V
illustrate a case where a thermistor supplied by REF5V is connected to Pin 3 to detect excessive temperatures of the application
(refer to application schematic).
NCP1239
capacitor, it
CC
= V
.
CC
CCOFF
decreases from
CC
V
CCON
V
CCOFF
Latch−off phase level
Logic reset level
Stop!
Figure 43.
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In fact, Tpulse is generally:
− shorter than the switching phase period. In this
case, t1 is longer since the latched off phase starts
earlier (at a V
consequence, the final duty cycle is lower than
previously estimated,
− longer than the switching phase period. In this case,
the circuit detects an overload condition simply
because V
CC
the fault timer has elapsed. Tpulse is lower than 100
ms and as a result the duty cycle is also lower.
(Major) Fault Detection and Latched Off Mode
The NCP1239 features a fast comparator that
permanently monitors the "Fault Detect" pin level. If for any
reason this level exceeds 2.4 V (typical), the part
immediately stops oscillating and stays latched off until the
user cycles down the power supply. This enables the SMPS
designer to externally shut down the part in particular when
a major default occurs, e.g. an Overvoltage Protection
(OVP). Figure 43 shows what happens when the part is
latched:
The user has unplugged, reset!
2.4 V
24
higher than V
CC
CCOFF
drops below V
(11.2 V) before
CCOFF
goes below 4 V. The figure can
CC
). As a
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