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Skipping Cycle Mode
The NCP1239 automatically skips switching cycles when
the output power demand drops below a given level. This is
accomplished by monitoring the FB pin. In normal
operation, Pin 8 imposes a current setpoint accordingly to
the load value. If the load demand decreases, the internal
loop asks for less peak current. When this setpoint reaches
a fixed determined level, the IC prevents the current from
decreasing further down and starts to blank the output
pulses: the IC enters the so−called skip−cycle mode, also
named controlled burst operation. The default skip−cycle
current is internally frozen to 30% of the maximum peak
current which is 0.5 V/Rsense The power transfer now
depends upon the width of the pulse bunches (Figure 54).
When FB is below the skip−cycle threshold (0.43 V by
default), the circuit skips the switching cycle. When the IC
enters the skip−cycle mode, the peak current cannot go
FB Pin Voltage
Normal current mode operation
Skip−cycle operation
Ip
= 150 mV/Rsense
MIN
Output pulses at various power levels (X = 5ms/div) P1 < P2 < P3
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NCP1239
Suppose we have the following component values:
Lp, primary inductance = 350 mH
fsw , switching frequency = 65 kHz
Ip skip = 600 mA (or 140 mV/Rsense)
The theoretical power transfer is therefore:
2
1/2 * Lp * Ip
* fsw = 4 W
If this IC enters skip−cycle mode with a bunch length of
10 ms over a recurrent period of 100 ms, then the total power
transfer is:
4 W * 10 ms/100 ms = 400 mW
To better understand how this skip−cycle mode takes
place, a look at the operation mode versus the FB level
immediately gives the necessary insight:
Figure 54.
below (0.43 V/3)/Rsense or 140 mV/Rsense. Figure 55
shows different values of pulse widths when the SMPS starts
to skip−cycles at different power levels:
Figure 55.
33
4.3 V, FB Pin open
2.7 V upper dynamic range
0.43 V
Power P1
Power P2
Power P3
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