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NCP1239
INFORMATIVE WAVEFORMS
The following plots were obtained using a 150 W application (output 19 V/7 A).
The NCP1239 enables the PFC V
as soon as the FB pin voltage has gone below a threshold (about 2.7 V), that is when the
CC
internal error flag stops being asserted.
Figure 60. Startup Sequence
The feedback voltage goes high and asserts the internal error flag. The Pin 6 timer counts for about 100 ms (C
= 390 ns)
pin6
before shutting down the SMPS. One "V
cycle over two is skipped" to limit the duty cycle in overload.
CC
Figure 61. Overload Conditions
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