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Figure 37 depicts the V
CC
Vcc
VccON
VccOFF
FB
Full power
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Error
7.5ms*
Flag
SS
Timer
*This time is programmed by the Pin 6 capacitor. C
− Soft−Start Time (T
− Jittering Period (T
− Fault Detection Delay (T
More generally, the times approximately depend on C
− T
= 7.5 ms * C
ss
− T
jittering
− T
delay
evolution during a proper startup sequence, showing the state of the error flag:
Feedback loop
reacts...
regulation
Skip level
Ip max
No error has
been confirmed
):7.5 ms
ss
): 10 ms
jittering
): 100 ms
delay
/ 390 nF
pin6
=10 ms * C
/ 390 nF
pin6
=100 ms * C
/ 390 nF
pin6
http://onsemi.com
NCP1239
Latch−off phase level
Logic reset level
= 390 nF nearly sets the following intervals:
pin6
as follows:
pin6
Figure 37.
18
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