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ON Semiconductor NCP1239FDR2G Reference Manual

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NCP1239
Low−Standby High
Performance PWM Controller
Housed in SO−16 the NCP1239 represents a major leap toward
ultra−compact Switch Mode Power Supplies specifically tailored for
medium to high power off−line applications, e.g. notebook adapters.
The NCP1239 offers everything needed to build a rugged and efficient
power supply, including a dedicated event management to drive a
Power Factor Correction (PFC) front−end circuitry. The circuit
disables the front−end PFC stage while still in fault or standby
conditions by interrupting the PFC controller powering for improved
no−load consumption figures. As soon as normal operating mode
recovers, the NCP1239 feeds back the PFC that wakes−up.
When power demand is low, the IC automatically enters the
so−called skip−cycle mode and provides excellent efficiency at light
loads. Because this occurs at a user adjustable low peak current, no
acoustic noise takes place.
Features
•
Current−Mode Operation with Internal Ramp Compensation
•
Internal High−Voltage Current Source for loss−less Startup
•
Adjustable Skip−Cycle Capability
•
Selectable Soft−Start Period
•
Internal Frequency Dithering for Improved EMI Signature
•
Go−to−Standby Signal for PFC Front−Stage
•
Large V
Operation from 12.2 V to 36 V
CC
•
500 mV Overcurrent Limit
•
500 mA/−800 mA Peak Current Capability
•
5 V/10 mA Pinned−out Reference Voltage
•
Adjustable Switching Frequency up to 250 kHz.
•
Overload Protection Independent of the Auxiliary V
•
Adjustable Over Power Compensation (NCP1239F)
•
Programmable Maximum Duty Cycle (NCP1239V)
•
Pb−Free Packages are Available*
Typical Applications
•
High Power AC/DC Adapters for Notebooks etc.
•
Offline Battery Chargers
•
Telecom and PC Power Supplies
•
Flyback Applications (NCP1239F) and Forward Applications
(NCP1239V)
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
October, 2005 − Rev. 5
16
CC
Fault Detect
Skip Adjust
Fault Detect
Skip Adjust
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
1
http://onsemi.com
SO−16
FD or VD SUFFIX
CASE 751B
1
MARKING DIAGRAM
16
NCP1239xDG
AWLYWW
1
NCP1239xD = Device Code
x
= F or V
A
= Assembly Location
WL
= Wafer Lot
Y
= Year
WW
= Work Week
G
= Pb−Free Package
PIN CONNECTIONS
1
16
GTS
REF5V
Rt
Brown−out
SS/Timer
FB
NCP1239F
1
16
GTS
REF5V
Rt
Brown−out
SS/Timer
FB
NCP1239V
ORDERING INFORMATION
Publication Order Number
HV
NC
NC
V
CC
Drv
GND
CS
Over Power
Limit
HV
NC
NC
V
CC
Drv
GND
CS
Max Duty−
Cycle
NCP1239/D

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Summary of Contents for ON Semiconductor NCP1239FDR2G

  • Page 1 NCP1239V ORDERING INFORMATION *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques See detailed ordering and shipping information in the package Reference Manual, SOLDERRM/D. dimensions section on page 5 of this data sheet.
  • Page 2 NCP1239 Vbulk Rbo1 to PFC_V REF5V REF5V (5V/10mA) Thermistor Cbulk Rramp Rbo2 Rcomp NCP1239F Figure 1. NCP1239F Typical Application Example Vbulk Rbo1 to PFC_V REF5V REF5V (5V/10mA) Thermistor Cbulk Rramp Rbo2 NCP1239V Rdmax Figure 2. NCP1239V Typical Application Example http://onsemi.com...

  • Page 3: Maximum Ratings

    NCP1239 MAXIMUM RATINGS Rating Symbol Value Unit Power Supply Voltage Pins 1 to 10 (except Vref Pin) Maximum Voltage −0.3, +10 Maximum Voltage on Pin 16 (HV) °C/W Thermal Resistance, Junction−to−Air, SOIC Version °C Maximum Junction Temperature °C Storage Temperature Range −60 to +150 ESD Capability, HBM Model (All Pins except HV) ESD Capability...
  • Page 4 NCP1239 ELECTRICAL CHARACTERISTICS (For typical values T = 25°C, for min/max values T = 0°C to +125°C, V = 48 V, pin16 = 20 V unless otherwise noted.) Symbol Rating Unit Drive Output Output Voltage Positive Clamp 11.5 13.6 Output Voltage Rise−Time @ CL = 1 nF, 10−90% of output signal −...

  • Page 5: Ordering Information

    Vfault Fault Detection Threshold ORDERING INFORMATION † Device Package Shipping NCP1239FDR2 SOIC−16 2500 / Tape & Reel NCP1239FDR2G SOIC−16 2500 / Tape & Reel (Pb−Free) NCP1239VDR2 SOIC−16 2500 / Tape & Reel NCP1239VDR2G SOIC−16 2500 / Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging...

  • Page 6: Pin Function Description

    NCP1239 PIN FUNCTION DESCRIPTION Pin No. Pin Name Function Pin Description Shuts the PFC down in The standby detection block changes Pin 1 state in accordance to the mode standby (standby or normal mode). Pin1 is designed to drive an external pnp transistor that connects or disconnects the NCP1239’s V to the PFC’s.
  • Page 7 NCP1239 FB<Vpin1 => Skip high Skip − Stby_detect 100k Skip UVLOs adjust Latch 450mV Reset Internal − Thermal Shutdown FB>1.6*Vpin1 =>Stby_detect RESET UVLO Fault (Vcc<VccOFF) − detect 2.5V Fault regOUT Regul Vcc < 4V PFC_Vcc stdwn pfcON pfcOFF Stby Startup Phase Vstop Divider by 2 Vcc<7V...
  • Page 8 NCP1239 FB<Vpin1 => Skip high Skip − Stby_detect 100k Skip UVLOs adjust 450mV Latch Reset Internal − Thermal Shutdown FB>1.6*Vpin1 =>Stby_detect RESET UVLO Fault (Vcc<VccOFF) − detect 2.5V Fault regOUT Regul Vcc < 4V PFC_Vcc stdwn pfcON pfcOFF Stby Startup Phase Vstop Vcc<7V Divider by 2...

  • Page 9: Typical Performance Characteristics

    NCP1239 TYPICAL PERFORMANCE CHARACTERISTICS −25 −25 TEMPERATURE (°C) TEMPERATURE (°C) Figure 5. High Voltage Current Source Figure 6. Startup Current Sourced by V vs. Temperature @ V = 10 V vs. Temperature @ V = 10 V −25 TEMPERATURE (°C) TEMPERATURE (°C) Figure 8.
  • Page 10 NCP1239 TYPICAL PERFORMANCE CHARACTERISTICS 6.95 6.90 6.85 6.80 6.75 −25 −25 TEMPERATURE (°C) TEMPERATURE (°C) Figure 11. V Latched−Off vs. Temperature Figure 12. No Load Circuit Consumption vs. Temperature 260 kHz 130 kHz 100 kHz 200 kHz 65 kHz 130 kHz −25 −25 TEMPERATURE (°C)
  • Page 11 NCP1239 TYPICAL PERFORMANCE CHARACTERISTICS −25 −25 TEMPERATURE (°C) TEMPERATURE (°C) Figure 17. Driver High State Voltage Drop Figure 18. Driver Sink Resistance vs. Temperature vs. Temperature −25 −25 TEMPERATURE (°C) TEMPERATURE (°C) Figure 19. Driver Voltage Clamp vs. Temperature Figure 20. Maximum Duty Cycle vs. Temperature (NCP1239F) 12300 6700...
  • Page 12 NCP1239 TYPICAL PERFORMANCE CHARACTERISTICS 0.508 0.506 BO = 2 V 0.504 0.502 0.500 0.498 0.496 BO = 1 V 0.494 0.492 −25 −25 TEMPERATURE (°C) TEMPERATURE (°C) Figure 23. Pin 9 Current vs. Temperature Figure 24. Over Power Limitation Threshold vs. (@ V = 0.5 V) (NCP1239F) Temperature (NCP1239F)
  • Page 13 NCP1239 TYPICAL PERFORMANCE CHARACTERISTICS 2.51 0.245 0.244 2.49 0.243 2.47 0.242 2.45 0.241 2.43 0.240 0.239 2.41 0.238 2.39 0.237 2.37 0.236 0.235 2.35 −25 −25 TEMPERATURE (°C) TEMPERATURE (°C) Figure 29. Brown−Out Low Threshold vs. Figure 30. Fault Detect Threshold vs. Temperature Temperature 24.5 1.35...

  • Page 14: Fault Management

    NCP1239 Fault Management New Startup Fault confirmed Fault not confirmed attempt 100ms* 100ms* 4.3V 10ms* Jittering 3.0V 1.8V fmax fmin OVL signal (Over−Load) 0.9 V 0.9 V 0.9 V Error flag Error flag Error flag Reset at UVLO PFC off PFC off PFC on 16.4V...
  • Page 15 NCP1239 Standby Detection Standby is not confirmed Standby is confirmed, Vpin6 4.3V (SS/timer) Jittering 10ms* 3.0V 1.8V 100ms* 100ms* delay PFC is down PFC running Bunches of pulses No delay FB−stby−out (1.7*Vpin7) FB−skip (Vpin7) Skip activity Fb is ok Stby_detect latch is armed Stby_detect latch is reset Standby is entered Standby is left...

  • Page 16: Application Information

    NCP1239 APPLICATION INFORMATION The NCP1239 includes all necessary features to help detected mode (standby or normal mode). Simply connect a building a rugged and safe switch−mode power supply. The pnp transistor between the NCP1239 V and the PFC following details the major benefits brought by controller one and drive it using Pin 1, to enable the PFC implementing the NCP1239 controller: stage in normal mode and disable it in standby.

  • Page 17: Startup Sequence

    NCP1239 Startup Sequence As soon as V reaches 16.4 V, driving pulses are When the power supply is first connected to the mains delivered on Pin 12 and the auxiliary winding grows up the outlet, the internal current source (typically 3.6 mA) is pin.
  • Page 18 NCP1239 Figure 37 depicts the V evolution during a proper startup sequence, showing the state of the error flag: VccON VccOFF Latch−off phase level Logic reset level Feedback loop Full power reacts... User regulation Powers up! Skip level Ip max Error 7.5ms* Flag...
  • Page 19 NCP1239 PFC Startup Sequence internal 0.9 V Zener diode actively clamping the current To ensure an adequate startup sequence of both PWM amplitude to (0.9 V/Rsense). During this time, the NCP1239 section and the PFC stage, some logic and timing need to be asserts an error flag.
  • Page 20 NCP1239 regulation Short−circuit Short−circuit Stby stby is left 16.4V Pout 11.2V 6.9V Timer 100ms* 100ms* 100ms* 100ms* One Vcc cycle is skipped to lower the burst mode duty cycle to typically 5% in fault conditions. 0.9V flag 7.5ms* If the fault had disappeared the SMPS would recover normal operation Standby...
  • Page 21 NCP1239 The PFC controller connection is really straightforward as away as it is fully supplied by the PWM auxiliary winding testified by Figure 39: simply connect to Pin 1, the base of and even high quiescent current devices do not hamper the a pnp transistor that connects the PFC’s V to the NCP1239 standby power since they are completely disconnected in...
  • Page 22 NCP1239 Leakage effect: 25.0 Vpeak = 24.2V ”clean” plateau V = 13.4V 15.0 5.00 5.00 − 15.0 − 236U 240U 244U 248U 252U The leakage effect seen on the auxiliary side pulls−up the final level peak−rectified by the diode Figure 40. On Figure 40’s example, one can clearly observe the elapsed, nothing happens and the controller continues difference between the peak and the real plateau DC level.
  • Page 23 NCP1239 = 390 nF pin6 CCON CCOFF 100ms < 100ms Bunch length given by timer Bunch length given by VccOFF When V drops faster than the timer, it prematurely interrupts the pulses flow. The 100 ms delay could be shortened or lengthened by changing the Pin 6 capacitor. Figure 41.
  • Page 24 NCP1239 If by design we have selected a 47 mF V capacitor, it In fact, Tpulse is generally: becomes easy to evaluate the burst period and its duty−cycle. − shorter than the switching phase period. In this This can be done by properly identifying all time events on case, t1 is longer since the latched off phase starts Figure 42 and applying the classical formula: t = C * DV / i.
  • Page 25 NCP1239 Pin 3 can serve to build an Overvoltage Protection by example, one can take as the temperature limit the placing a Zener between the voltage to measure (e.g., V application must not exceed. Choosing R equal to 5k, the and Pin 3 (refer to application schematic).
  • Page 26 NCP1239 Figure 45 offers a way to connect the elements around Pin 5 to create a Brown−Out detection: to converter Preconverter Rupper Input AC line Filtering Cbulk Capacitor Rlower Cfil Example where the voltage of the bulk capacitor is used for the brown−out Protection Figure 45.
  • Page 27 NCP1239 bulk VBulk Cbulk V(line)*V(timing) Bload 47uF Vline Voltage Current IC = 40 V(CMP) > 3, 35/V (bulk) : 0 − PSpice: EBload Value = { IF ( V(CMP)>3, 35/V(bulk), 0) } bulk line timing Rupper 2.4Meg BrownOut − Cfil Rlower Bbrown 220n...
  • Page 28 NCP1239 Rectified AC Line Sensing to converter Preconverter Rupper Input filtering ac line Capacitor Cbulk Rlower Cfil A second option to directly sense the mains Figure 48. This second option that directly senses the input voltage In addition, it is not recommended to provide the output (see Figure 48), enables a more direct under−mains with more power than normally necessary.
  • Page 29 NCP1239 Actual Peak Current Low Input Voltage Vopl/Rsense Wished Maximum High Input Peak Current Voltage at low line, DI The propagation delay (Dt) produces overcurrents (DI at high line in the figure) that are proportional to the input voltage. As a consequence, the actual maximum current and then the power limit gets higher when the AC line increases. Figure 49.
  • Page 30 NCP1239 Rbo1 pin5 80mA/V*V pin5 Rbo2 Brown−Out to Brown−Out Comparator = k*R comp comp pin5 Rcomp − Over Power comp Limit Rsense 0.5V Rramp Current Sense Comparator Current Sense An (averaged) portion of the input voltage is applied to the brown−out pin. A current source proportional to this voltage, flows through an external resistor Rcomp to form an offset proportional to the (average) input voltage.

  • Page 31: Soft Start

    NCP1239 Soft−Start regulation. The soft−start is also activated at each start of the The NCP1239 features an internal soft−start activated active phase of fault burst operation. Every restart attempt during the Power On sequence (PON). As soon as V is followed by a soft−start activation. reaches 16.4 V, the current setpoint is gradually increased Generally speaking, the soft−start will be activated when from nearly zero up to the maximum clamping level (e.g.

  • Page 32: Frequency Jittering

    NCP1239 In the NCP1239, the ramp features a swing of 3.2 V. The ramp is disabled during standby (i.e., when pfcON is Suppose we select a 65 kHz version. Over a 65 kHz low). This inhibition avoids that the ramp compensation frequency, it corresponds to a 130 mV/ms ramp.
  • Page 33 NCP1239 Skipping Cycle Mode Suppose we have the following component values: Lp, primary inductance = 350 mH The NCP1239 automatically skips switching cycles when the output power demand drops below a given level. This is fsw , switching frequency = 65 kHz accomplished by monitoring the FB pin.
  • Page 34 NCP1239 Max peak 300.0M current 200.0M 25% of max Ip 100.0M 315.4U 882.7U 1.450M 2.017M 2.585M The skip−cycle takes place at low peak currents which guaranties noise free operation Figure 56. PFC Inhibition in Standby Pin 7). A timer counts down and if COMP2 keeps high for The circuit detects a light load condition by permanently 100 ms (typically with 390 nF on Pin 6), the NCP1239 monitoring the skip−cycle comparator activity: in normal...
  • Page 35 NCP1239 One clearly sees that the GTS signal does not react to the fugitive low FB Pin condition during startup Figure 58. FB < V => Skip high pin7 REF5V Skip Skip − Adjust Stby_detect 100k COMP1 0.43V COMP2 − FB >...
  • Page 36 NCP1239 INFORMATIVE WAVEFORMS The following plots were obtained using a 150 W application (output 19 V/7 A). The NCP1239 enables the PFC V as soon as the FB pin voltage has gone below a threshold (about 2.7 V), that is when the internal error flag stops being asserted.
  • Page 37 NCP1239 When the load current falls to a low level (CH4), the FB pin voltage diminishes to take into account the decay of the power demand. As a consequence, the FB pin voltage goes below the “Vskip” threshold and the soft start timer counts about 100 ms (if C = 330 nF).

  • Page 38: Package Dimensions

    Literature Distribution Center for ON Semiconductor USA/Canada Order Literature: http://www.onsemi.com/litorder P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Japan: ON Semiconductor, Japan Customer Focus Center Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada For additional information, please contact your 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada...

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