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100k
Skip
7
adjust
+
450mV
25r
FB>1.6*Vpin1 =>Stby_detect RESET
Fault
3
−
detect
+
2.5V
Vcc
10k
PFC_Vcc
1
pfcON
1mA
Vdd
6
SS / timer
2
REF5V
+
5V
BO_in
BO
5
+
0.5V / 0.25V
Vdd
4
Rt
2.5V
Vdd
20k
FB
8
to Skip
NCP1239
FB<Vpin1 => Skip high
Skip
+
−
FB
S
Q
15r
Q
R
+
−
S
Fault
Q
Q
R
Vcc < 4V
pfcOFF
Stby
Startup Phase
Vdd
OVL
Soft−Start
and timer
management
Soft−Start
Jittering
Ipk limit
Modulation
Ramp
3.2V
Compensation
−
BO_out
+
Vstop
Oscillator
CLK
−
+
Jittering
Modulation
"Jittered"
Reference
/ 3
Soft−Start
Ipk limit
Figure 3. NCP1239F Internal Circuit Architecture
http://onsemi.com
Stby_detect
UVLOs
Latch
Reset
Internal
Thermal
Shutdown
UVLO
TSD
OVL
regOUT
Vdd
stdwn
Vstop
S
Q
Q
R
Divider by 2
Stby_detect
Error_Flag
OUTon
pfcON
32k
CLK
S
Q
Q
R
Skip
−
+
+
+
−
0.5V
0.9V
Error flag
7
HV
16
15
(Vcc<VccOFF)
14
Regul
13
Vcc
Vcc<7V
Output
Buffer
Drv
12
14V
clamp
11
GND
10
LEB
CS
Vdd
BO_in
75 mA/V x V
pin5
9
Over Power
Limit
LEB
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