u-blox LARA-R2 series System Integration Manual page 72

2.2.1.6 Additional guidelines for VCC supply circuit design
To reduce voltage drops, use a low impedance power source. The series resistance of the power supply lines
(connected to the VCC and GND pins of the module) on the application board and battery pack should also be
considered and minimized: cabling and routing must be as short as possible to minimize power losses.
Three pins are allocated for VCC supply. Several pins are designated for GND connection. It is recommended to
properly connect all of them to supply the module to minimize series resistance losses.
In case of modules supporting 2G radio access technology, to avoid voltage drop undershoot and overshoot at
the start and end of a transmit burst during a GSM call (when current consumption on the VCC supply can rise
up as specified in the LARA-R2 series Data Sheet [1]), place a bypass capacitor with large capacitance (at least
100 µF) and low ESR near the VCC pins, for example:

330 µF capacitance, 45 m ESR (e.g. KEMET T520D337M006ATE045, Tantalum Capacitor)
To reduce voltage ripple and noise, improving RF performance especially if the application device integrates an
internal antenna, place the following bypass capacitors near the VCC pins:

68 pF capacitor with Self-Resonant Frequency in 800/900 MHz range (e.g. Murata GRM1555C1E560J)

15 pF capacitor with Self-Resonant Frequency in 1800/1900 MHz range (e.g. Murata GRM1555C1E150J)

8.2 pF capacitor with Self-Resonant Frequency in 2500/2600 MHz range (e.g. Murata GRM1555C1H8R2D)

10 nF capacitor (e.g. Murata GRM155R71C103K) to filter digital logic noise from clocks and data sources

100 nF capacitor (e.g Murata GRM155R61C104K) to filter digital logic noise from clocks and data sources
A suitable series ferrite bead can be properly placed on the VCC line for additional noise filtering if required by
the specific application according to the whole application board design.
LARA-R2 series
VCC
51
VCC 52
VCC 53
GND
Figure 30: Suggested schematic for the VCC bypass capacitors to reduce ripple / noise on supply voltage profile
Reference Description
C1 8.2 pF Capacitor Ceramic C0G 0402 5% 50 V
C2 15 pF Capacitor Ceramic C0G 0402 5% 50 V
C3 68 pF Capacitor Ceramic C0G 0402 5% 50 V
C4 10 nF Capacitor Ceramic X7R 0402 10% 16 V
C5 100 nF Capacitor Ceramic X7R 0402 10% 16 V
C6
330 µF Capacitor Tantalum D_SIZE 6.3 V 45 m
Table 23: Suggested components to reduce ripple / noise on VCC
The necessity of each part depends on the specific design, but it is recommended to provide all the bypass
capacitors described in Figure 30 / Table 23 if the application device integrates an internal antenna.
ESD sensitivity rating of the VCC supply pins is 1 kV (Human Body Model according to JESD22-A114).
Higher protection level can be required if the line is externally accessible on the application board, e.g. if
accessible battery connector is directly connected to VCC pins. Higher protection level can be achieved by
mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) close to accessible point.
UBX-16010573 - R02
C1 C2 C3 C4 C5
Recommended for Recommended for
cellular modules
supporting LTE band-7
LARA-R2 series - System Integration Manual
3V8
+
C6
cellular modules
supporting 2G
Part Number - Manufacturer
GRM1555C1H8R2DZ01 - Murata
GRM1555C1H150JA01 - Murata
GRM1555C1H680JA01 - Murata
GRM155R71C103KA01 - Murata
GRM155R71C104KA01 - Murata
T520D337M006ATE045 - KEMET
Objective Specification Design-in
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