Silicon Laboratories SI5324 Specification Sheet page 2

Video Timing Solutions
A N Y - R A T E F R E Q U E N C Y
F L E X I B I L I T Y
High Performance
The Si5324 is the industry's lowest jitter
genlock clock IC. The device provides any-
rate frequency synthesis simplifying HD
video and audio clock generation. With
jitter performance of 5 ps pk-pk, the Si5324
delivers significant jitter margin in 3G-SDI
serializer applications, reducing design risk
and improved link performance.
Highly Integrated
The Si5324 offers the industry's most
highly integrated video clock generator IC
requiring no external PLL components (low
pass filter, charge pump, or VCXO). Because
all PLL components are integrated, board-
level noise immunity is improved reducing
design risk versus traditional video clock IC
solutions.
Any-Rate Frequency Flexibility
The Si5324's any rate frequency flexibility
enables a single device to generate all
common genlock reference frequencies
required in next-generation SD/HD video
and audio equipment. The Si5324 is easily
reconfigurable via I2C/SPI interface and
requires no component changes for different
frequency plans, simplifying design reuse.
Recommended Silicon Labs Timing Solutions for Video
Any-Rate Jitter Attenuating Clock Multipliers, Clock Generators and Buffers
Input/
Part
Output Control
Number
Clocks
Si5324 2/2 Diff I 2 C or SPI
Si5368 4/5 Diff I 2 C or SPI
Si5338 4/4 Diff I 2 C or SPI
1:4 Diff
Si5330 Pin
1:8 SE
Single and Multi-Frequency Crystal-Based XO/VCXO
Part Number Type
Si530/1 XO
Si532/3 XO
Si534 XO
Si550 VCXO
Si552 VCXO
Si554 VCXO
Si570 XO Programmable Any-Rate
Si571 VCXO Programmable Any-Rate
Si590/1 XO
Si595 VCXO
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their respective owners. For the most up to date information please see your sales representative or visit our website at www.silabs.com.
100, August 09, Rev A SOL-VTS-2009A
Industry's Most Integrated Genlock Solution
Silicon Labs' Si5324 replaces multi-component video clock ICs, external loop fi lter and
VCXO components with a single IC, simplifying genlock designs.
Traditional Video Clock Solution
HSYNC
SDI
Reference
Industry's Only Quad and Any-Rate Frequency XO/VCXOs
Built to Order Samples
Silicon Labs offers an easy-to-use web utility to build and confi gure the
right XO/VCXO for your application. Samples of any frequency XO/VCXO
are available in less than two weeks. www.silabs.com/BuyXO
Input Frequency Output Frequency
2 kHz to 710 MHz 2 kHz to 1.4 GHz
2 kHz to 710 MHz 2 kHz to 1.4 GHz
8 to 30 MHz (xtal) 160 kHz to
160 kHz to 710 MHz (clock) 710 MHz
5 to 710 MHz Diff 5 to 710 MHz Diff
5 to 350 MHz SE 5 to 350 MHz SE
Frequency Control Frequency Range
Single Pin
Dual Pin
1213 to 1417 MHz
Quad Pin
Single Pin
Dual Pin
1213 to 1417 MHz
Quad Pin
2
I C
2
I C
Single Pin
Single Pin
Loop
Crystal
Filter VCXO
Video
PLL with
3G-SDI
Jitter
Genlock
Cleaner
Clock
Minimum
Jitter PLL
Bandwidth
5 ps pk-pk 4 Hz
8 ps pk-pk 60 Hz
36 ps pk-pk 1.6 MHz
55 fs rms —
Jitter Stability/APR Options (ppm)
10 to 945 MHz
970 to 1134 MHz 0.3 ps rms
10 to 945 MHz
970 to 1134 MHz 0.5 ps rms
10 to 280 MHz
0.3 ps rms
10 to 810 MHz
0.5 ps rms
10 to 1417 MHz
0.7 ps rms
10 to 525 MHz
0.7 ps rms
Silicon Laboratories Inc.
400 West Cesar Chavez • Austin, TX 78701
Toll Free: (877) 444-3032
Email: ClockInfo@silabs.com or
Web site: www.silabs.com
www.silabs.com/Timing
vs. Silicon Labs Solution
Crystal
HSYNC
SDI
Reference
Si534 XO/Si554 VCXO
• Eliminates multiple oscillators,
reduces system cost
• Simplifies BOM and saves board
space and inventory
• Ideal for multi-rate FPGA-based PLLs
Jitter Clock
Attenuation Generation Distribution
• •
• •
•
Kv Options (ppm/V)
N/A
±20
±31.5 N/A
±61.5
N/A
±12 to ±375 33 to 356
±31.5; ±61.5 N/A
±12 to ±375 33 to 356
±30; ±50; ±100 N/A
±10 to ±370 45 to 380
VCXOInfo@silabs.com
3G-SDI
Clock
SD
Clock
Clock
Package
• 36-QFN
• 100-TQFP
• 24-QFN
• 24-QFN
Package
6-pad
6-pad
8-pad
6-pad
6-pad
8-pad
8-pad
8-pad
6-pad
6-pad