Pin Description - Siemens SPC3 Hardware Description

3 Pin Description

The SPC3 has a 44-pin PQFP housing with the following signals:
Pin Signal Name
1 XCS
2 XWR/E_Clock
3 DIVIDER
4 XRD/R_W
5 CLK
6 VSS
7 CLKOUT2/4
8 XINT/MOT
9 X/INT
10 AB10
11 DB0
12 DB1
13 XDATAEXCH
14 XREADY/XDTACK
15 DB2
16 DB3
17 VSS
18 VDD
19 DB4
20 DB5
21 DB6
22 DB7
23 MODE
24 ALE/AS
25 AB9
26 TXD
27 RTS
28 VSS
29 AB8
30 RXD
31 AB7
32 AB6
33 XCTS
34 XTEST0
35 XTEST1
36 RESET
37 AB4
38 VSS
39 VDD
40 AB3
41 AB2
42 AB5
43 AB1
44 AB0
Figure 3.1: SPC3 Pin Assignment
Note: All signals that begin with X.. are LOW active
VDD = +5V, VSS = GND
Input levels: I ©:
I (CS):
SPC3 Hardware Description
Copyright (C) Siemens AG 2003 All rights reserved.
SPC3
In/Out Description
I© Chip-Select
I© Write signal /EI_Clock for Motorola
I© Setting the scaler factor for CLK2OUT2/4.
low potential means divided through 4
I© Read signal / Read_Write for Motorola
I(TS) Clock pulse input
O Clock pulse divided by 2 or 4
I© <log> 0 = Intel interface
<log> 1 = Motorola interface
O Interrupt
I(CPD) Address bus
I©/O Data bus
I©/O
O Data_Exchange state for PROFIBUS-DP
O Ready for external CPU
I©/O Data bus
I©/O
I©/O Data bus
I©/O
I©/O
I©/O
I <log> 0 = 80C166 Data bus/address bus separated; ready signal
<log> 1 = 80C32 data bus/address bus multiplexed, fixed timing
I© Address latch enable C32 mode: ALE
I Address bus
O Serial send port
O Request to Send
I© Address bus
I© Serial receive port
I© Address bus
I© Address bus
I© Clear to send <log> 0 = send enable
I© Pin must be placed fixed at VDD.
I© Pin must be placed fixed at VDD.
I(CS) Connect reset input with CPU's port pin.
I© Address bus
I©
I© Address bus
I©
I© Address bus
I©
CMOS
CMOS Schmitt trigger
PROFIBUS Interface Center
C32 Mode: place on VDD.
C165 Mode: CS-Signal
C32 mode: <log> 0
C165 mode: address bus
C32 Mode: Data/address bus multiplexed
C165 Mode: Data/address bus separated
C32 mode: data bus/address
bus multiplexed
C165 mode: data/address bus
separate
C32 mode: data bus/address
bus multiplexed
C165 mode: data bus/address
bus separate
C165 mode: <log> 0
C32 mode: <log> 0
C165 mode: address bus
C32 Mode : <log> 0
C165 Mode: address bus
V1.3
Source / Destination
CPU (80C165)
CPU
CPU
System
System, CPU
System
CPU, Interrupt-Contr.
CPU, memory
LED
System, CPU
CPU, memory
CPU, memory
System
CPU (80C32)
CPU (C165), memory
RS 485 sender
RS 485 sender
RS 485 receiver
System, CPU
System, CPU
FSK modem
System, CPU
System, CPU
System, CPU
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2003/04