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The request for a read access to SPC3 is derived from the positive edge of the E clock (in addition: XCS =
0, R W = 1). The request for a write access is derived from the negative edge of the E clock (in addition:
XCS = 0, R W = 0).
No.
40
E_Clock-Pulse-Width
41
Address (AB
) Setuptime to E_Clock
10..0
42
Address (AB
) Holdtime after E_Clock
10..0
43
E_Clock
to Data Active Delay
44
E_Clock
to Data valid (Zugriff auf RAM)
E_Clock
to Data valid (Zugriff auf die Register)
45
Data Holdtime after E_Clock
46
R_W Setuptime to E_Clock
47
R_W Holdtime after E_Clock
48
XCS Setuptime to E_Clock
49
XCS Holdtime after E_Clock
50
Data Setuptime to E_Clock
51
Data Holdtime after E_Clock
Explanations:
T
=
Clock pulse cycle (48MHz)
TBD
=
to be defined
(1
=
Access to the RAM
(2
=
Access to the registers/latches
(3
=
For T = 48 MHz
Synchronous Motorola-Mode, Processor-Read-Timing
E_Clock
AB(10..0)
DB(7..0)
R_W
XCS
SPC3 Hardware Description
Copyright (C) Siemens AG 2003 All rights reserved.
SPC3
Parameter
41
46
48
PROFIBUS Interface Center
AMI-Vers.
Min
Max
8.5.4.1.1.1
T
+
74.2
10
5
5.7
17
4T + 5
(88,3)
4T + 18
(101,3)
2
6.3
10
5
0
0
10
10
40
44
VALID
43
Data Invalid
Data Valid
V1.3
ST-Vers.
Min
Max
Unit
3T + 74.2
ns
10
ns
5
ns
5
ns
3T + 44.2
ns
(107)
4T + 21.9
ns
(105,2)
4
12
ns
10
ns
5
ns
0
ns
0
ns
10
ns
10
ns
42
45
47
49
AS = log.'1'
Page 51
2003/04
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