Main Analog-To-Digital Converter; Reference Channel - Ametek 7280 Instruction Manual

bandwidth.
It should be noted that the dynamic range of a lock-in amplifier is normally so high
that practical anti-alias filters are not capable of completely removing the effect of a
full-scale alias. For instance, even if the filter gives 100 dB attenuation, an alias at the
input limit and at the reference frequency will give a one percent output error when
the dynamic reserve is set to 60 dB, or a ten percent error when the dynamic reserve
is set to 80 dB.
In a typical low-level signal recovery situation, many unwanted inputs need to be
dealt with and it is normal practice to make small adjustments to the reference
frequency until a clear point on the frequency spectrum is reached. In this context an
unwanted alias is treated as just another interfering signal and its frequency is
avoided when setting the reference frequency.
A buffered version of the analog signal just prior to the main ADC is available at the
signal monitor (SIG MON) connector on the rear panel; it may be viewed on an
oscilloscope to monitor the effect of the line frequency rejection and anti-aliasing
filters and signal-channel amplifiers.

3.3.06 Main Analog-to-Digital Converter

Following the anti-alias filter the signal passes to the main analog-to-digital converter
running at a sampling rate of 7.5 MHz. The output from the converter feeds the
demodulator circuitry, which uses DSP techniques to implement the digital
multipliers and the first stage of the output low-pass filtering for each of the X and Y
channels.
The ADC output also passes to the output processor to allow the power spectral
density of the input signal to be calculated using a discrete Fourier transform, which
in many ways is similar to a fast Fourier transform (FFT). The results of this
calculation are shown on the Spectral Display menu.
However, before discussing the demodulators and the output stages of the lock-in
amplifier, the reference channel which provides the other input to the demodulators,
will be described.

3.3.07 Reference Channel

The reference channel in the instrument is responsible for implementing the reference
trigger/phase-locked loop, digital phase-shifter and internal oscillator look-up table
functional blocks on the block diagram (see figure 3-1). The processor generates a
series of phase values, output at a rate of one every 133 ns, which are used to drive
the reference channel inputs of the demodulators.
In dual reference mode operation, an externally derived reference frequency is
connected to the external reference input and a second reference is derived from the
internal oscillator. The reference circuit generates new phase values for each
individual channel and sends these to the demodulators. Further discussion of dual
reference mode occurs in section 3.3.12.
In single harmonic mode, the reference circuit generates the phase values of a
Chapter 3, TECHNICAL DESCRIPTION
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