Anti-Aliasing Filter - Ametek 7280 Instruction Manual

Wide bandwidth dsp lock-in amplifier
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Chapter 3, TECHNICAL DESCRIPTION

3.3.05 Anti-Aliasing Filter

3-6
reserve is often expressed in decibels, for which
DR(in
dB)
Applying this formula to the model 7280 at the maximum value of INPUT LIMIT
(1.6 V) and the smallest available value of FULL-SCALE SENSITIVITY (10 nV),
gives a maximum available dynamic reserve of about 1 × 10
this magnitude are available from any DSP lock-in amplifier but are based only on
arithmetical identities and do not give any indication of how the instrument actually
performs. In fact, all current DSP lock-in amplifiers become too noisy and inaccurate
for most purposes at reserves of greater than about 100 dB.
For the benefit of users who prefer to have the AC Gain value expressed in decibels,
the model 7280 displays the current value of Dynamic Reserve (DR) in this form, on
the input full-scale sensitivity control, for values up to 100 dB. Above 100 dB the
legend changes to "DR>100".
Prior to the main analog-to-digital converter (ADC) the signal passes through an anti-
aliasing filter to remove unwanted frequencies which would cause a spurious output
from the ADC as a result of the sampling process.
Consider the situation when the lock-in amplifier is measuring a sinusoidal signal of
frequency f
Hz, which is sampled by the main ADC at a sampling frequency
signal
f
Hz. In order to ensure correct operation of the instrument the output values
sampling
representing the f
frequency must be uniquely generated by the signal to be
signal
measured, and not by any other process.
However, if the input to the ADC has, in addition, an unwanted sinusoidal signal
with frequency f
Hz, where f
1
will appear in the output as a sampled-data sinusoid with frequency less than half the
sampling frequency, f
alias
indistinguishable from the output generated when a genuine signal at frequency f
is sampled. Hence if the frequency of the unwanted signal were such that the alias
signal frequency produced from it was close to, or equal to, that of the wanted signal
then it is clear that a spurious output would result.
For example, if the sampling frequency were 7.5 MHz then half the sampling
frequency would be 3.75 MHz. Assume for a moment that the instrument could
operate at reference frequencies up to 3.75 MHz and let it be measuring a signal of
40 kHz accompanied by an interfering signal of 3.7 MHz. The output of the ADC
would therefore include a sampled-data sinusoid of 40 kHz (the required signal) and,
applying the above formula, an alias signal of 0.05 MHz, or 50 kHz (i.e. |3.75 MHz -
3.7 MHz|). If the signal frequency were now increased towards 50 kHz then the
output of the lock-in amplifier would increasingly be affected by the presence of the
alias signal and the accuracy of the measurement would deteriorate.
To overcome this problem the signal is fed through the anti-aliasing filter which
restricts the signal bandwidth to an upper frequency of 2.0 MHz The filter is a
conventional elliptic-type, low-pass, stage, giving the lowest possible noise
=
×
20
log(DR(as
a
ratio
is greater than half the sampling frequency, then this
1
= |f
- nf
|, where n is an integer. This alias signal is
1
sampling
))
8
or 160 dB. Figures of
alias

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