Di Sample Clock Timing Options; Routing Di Sample Clock To An Output Terminal; Di Sample Clock Timebase Signal; Using An Internal Source - National Instruments cRIO-904 Series User Manual

Embedded compactrio controller with real-time processor and reconfigurable fpga
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receives a DI Sample Clock signal when the FIFO is full, it reports an overflow error to the
host software.
A sample consists of one reading from each channel in the DI task. DI Sample Clock signals
the start of a sample of all digital input channels in the task. DI Sample Clock can be generated
from external or internal sources as shown in the following figure.
Analog Comparison
80 MHz Timebase
20 MHz Timebase
13.1072 MHz Timebase
12.8 MHz Timebase
10 MHz Timebase
100 kHz Timebase

Routing DI Sample Clock to an Output Terminal

You can route DI Sample Clock to any output PFI terminal.

DI Sample Clock Timebase Signal

The DI Sample Clock Timebase signal is divided down to provide a source for DI Sample
Clock. DI Sample Clock Timebase can be generated from external or internal sources. DI
Sample Clock Timebase is not available as an output from the controller.

Using an Internal Source

To use DI Sample Clock with an internal source, specify the signal source and the polarity of
the signal. Use the following signals as the source:
it Sample Clock
ot Sample Clock
Counter n Internal Output
Frequency Output
DI Change Detection Output
Several other internal signals can be routed to DI Sample Clock. Refer to the "Device Routing
in MAX" topic in the NI-DAQmx Help or the LabVIEW Help for more information.
62 | ni.com | cRIO-904x User Manual
Figure 39. DI Sample Clock Timing Options
PFI
DI Sample Clock
Event
Timebase
Analog Comparison Event
Ctr n Internal Output
Sigma-Delta Module Internal Output
Programmable
Clock
Divider
PFI
Sample
Clock

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