Ai Sample Clock Signal; Routing The Sample Clock To An Output Terminal; Ai Sample Clock Timebase Signal; Ai Convert Clock Signal Behavior For Analog Input Modules - National Instruments NI cDAQTM-9138 User Manual

Chapter 2 Analog Input
• AI Reference Trigger
• AI Pause Trigger
Signals with an * support digital filtering. Refer to the
Input/Output and PFI, for more information.
Refer to the AI Convert Clock Signal Behavior For Analog Input Modules section for AI Convert
Clock signals and the cDAQ chassis.

AI Sample Clock Signal

A sample consists of one reading from each channel in the AI task. Sample Clock signals the
start of a sample of all analog input channels in the task. Sample Clock can be generated from
external or internal sources as shown in Figure 2-1.
PFI
Analog Comparison
Event
20 MHz Timebase
80 MHz Timebase
100 kHz Timebase

Routing the Sample Clock to an Output Terminal

You can route Sample Clock to any output PFI terminal. Sample Clock is an active high pulse
by default.

AI Sample Clock Timebase Signal

The AI Sample Clock Timebase signal is divided down to provide a source for Sample Clock.
AI Sample Clock Timebase can be generated from external or internal sources. AI Sample Clock
Timebase is not available as an output from the chassis.
AI Convert Clock Signal Behavior For Analog Input
Modules
Refer to the Scanned
and Slow Sample Rate Modules
C Series analog input modules.
2-2 | ni.com
Signal*
Signal*
Figure 2-1. AI Sample Clock Timing Options
Sigma-Delta Module Internal Output
AI Sample Clock
Timebase
Modules, Simultaneous Sample-and-Hold
sections for information about the AI Convert Clock signal and
PFI Filters
Analog Comparison Event
Ctr n Internal Output
Programmable
Clock
Divider
Modules,
section of Chapter 4,
PFI
AI Sample Clock
Sigma-Delta
Digital
Modules,