Epson E0C6001 Technical Manual page 125

Cmos 4-bit single chip microcomputer

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E0C6001 TECHNICAL SOFTWARE

II-44

EIT32 This register enables or masks the 32 Hz timer interrupt.

The CPU is interrupted if it is in the EI state when the

interrupt mask register (EIT32) is set to "1" and the inter-

rupt condition flag (IT32) is "1". (See Figure 3.8.2.)

EIT8 This register enables or masks the 8 Hz timer interrupt. The

CPU is interrupted if it is in the EI state when the interrupt

mask register (EIT8) is set to "1" and the interrupt condition

flag (IT8) is "1". (See Figure 3.8.2.)

EIT2

This register enables or masks the 2 Hz timer interrupt. The

CPU is intterrupted if it is in the EI state when the interrupt

mask register (EIT2) is set to "1" and the interrupt condition

flag (IT2) is "1". (See Figure 3.8.2.)

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