Epson E0C6001 Technical Manual page 55

E0C6001 TECHNICAL HARDWARE
EIT32, EIT8, EIT2
IT32, IT8, IT2 Interrupt factor flags (0EFH D0–D2)
TMRST
I-48
Interrupt mask registers (0EBH D0–D2)
These registers are used to mask the clock timer interrupt.
When 1 is written: Enabled
When 0 is written: Masked
Reading:
The interrupt mask register bits (EIT32, EIT8, EIT2) mask
the corresponding interrupt frequencies (32 Hz, 8 Hz, 2 Hz).
After an initial reset, these registers are all set to 0.
These flags indicate the status of the clock timer interrupt.
When 1 is read:
When 0 is read:
Writing:
The interrupt factor flags (IT32, IT8, IT2) correspond to the
clock timer interrupts (32 Hz, 8 Hz, 2 Hz). The software can
determine from these flags whether there is a clock timer
interrupt. However, even if the interrupt is masked, the
flags are set to 1 on the falling edge of the signal. These
flags can be reset when the register is read by the software.
Reading of interrupt factor flags is available at EI, but be
careful in the following cases.
If the interrupt mask register value corresponding to the
interrupt factor flags to be read is set to 1, an interrupt
request will be generated by the interrupt factor flags set
timing, or an interrupt request will not be generated. Be
very careful when interrupt factor flags are in the same
address.
After an initial reset, these flags are set to 0.
Clock timer reset (0F9H D2)
This bit resets the clock timer.
When 1 is written: Clock timer reset
When 0 is written: No operation
Reading:
The clock timer is reset by writing 1 to TMRST. The clock
timer starts immediately after this. No operation results
when 0 is written to TMRST.
This bit is write-only, and so is always 0 when read.
Valid
Interrupt has occurred
Interrupt has not occurred
Invalid
Always 0