Epson E0C6001 Technical Manual page 124

• Interrupt mask registers
The interrupt mask registers are registers that individually
specify whether to enable or mask the timer interrupt (2 Hz,
8 Hz, 32 Hz) or input interrupt (K00–K03).
The following are descriptions of the interrupt mask regis-
ters.
EIK00 to EIK03 This register enables or masks the K00–K03 input interrupt.
The interrupt condition flag (IK0) is set to "1" when the
contents of the input (K00–K03) become "1" and the data of
the corresponding interrupt mask register (EIK00–EIK03) is
"1". The CPU is interrupted if it is in the EI state (interrupt
flag [I] = "1"). (See Figure 3.8.1.)
<Input interrupt programing related precautions>
Fig. 3.8.3
Input interrupt timing
When using an input interrupt, if you rewrite the content of
the mask register, when the value of the input terminal
which becomes the interrupt input is in the active status
(input terminal = high status), the factor flag for input
interrupt may be set.
For example, a factor flag is set with the timing of
in Figure 3.8.3. However, when clearing the content of the
mask register with the input terminal kept in the high
status and then setting it, the factor flag of the input inter-
rupt is again set at the timing that has been set.
Consequently, when the input terminal is in the active
status (high status), do not rewrite the mask register (clear-
ing, then setting the mask register), so that a factor flag will
only set at the rising edge in this case. When clearing, then
setting the mask register, set the mask register, when the
input terminal is not in the active status (low status).
CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)
Port K input
Mask register
When the content of the mask register is rewritten, while
the port K input is in the active status. The input interrupt
factor flag is set at .
Active status
Factor flag set Not set
shown
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