Xilinx LogiCORE IP Product Manual page 20

Triple Rate SDI Interface
See the LogiCORE IP Virtex-6 FPGA Triple-Rate SDI User Guide (UG823) for more
information.
Table 2‐11: Triple Rate SDI Interface Signals
Signal Name
tx_rst
tx_clk
tx_ce
tx_din_rdy
tx_ds1a
tx_ds1b
tx_ds2a
tx_ds2b
tx_level_b_3g
tx_mode
tx_m
Ethernet Packets Received Interface
See the SMPTE 2022-5/6 reference design for more information.
Table 2‐12: Ethernet Packets Received Interface Signals
Signal Name
rx_rtp_pkt_recv
rx_rtp_seq_num
rx_rtp_pkt_buffered
rx_rtp_pkt_transmit
rx_vid_lock
LogiCORE IP SMPTE2022‐5/6 RX v2.1
PG033 December 18, 2012
Direction Width Description
In 1 Reset.
Clock input. It must have a frequency of 74.25 MHz or
In 1 74.25/1.001 MHz for HD-SDI, 148.5 MHz or 148.5/1.001 MHz
for 3G-SDI, and 148.5 MHz for SD-SDI mode.
Out 3 To tx_ce of Triple-Rate SDI
Out 1 To tx_din_rdy of Triple-Rate SDI
Out 10 To tx_ds1a of Triple-Rate SDI
Out 10 To tx_ds1b of Triple-Rate SDI
Out 10 To tx_ds2a of Triple-Rate SDI
Out 10 To tx_ds2b of Triple-Rate SDI
Out 1 To tx_level_b_3g of Triple-Rate SDI
Out 1 To tx_mode of Triple-Rate SDI
In HD-SDI and 3G-SDI modes, this output indicates which bit
rate is received. If this output is Low, it indicates a bit rate of
Out 1 1.485 Gb/s in HD-SDI mode and 2.97 Gb/s in 3G-SDI mode. If
this output is High, it indicates a bit rate of 1.485/1.001 Gb/s
in HD-SDI mode and 2.97/1.001 Gb/s in 3G-SDI mode.
Direction Width
Out 1
Out 16
Out 16
Out 1
Out 1
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Chapter 2: Product Specification
Description
Pulse indicating receiving of RTP packets
Sequence number of RTP packet received
Amount of RTP packets buffered
Pulse indicating consumption of RTP packet for SDI
output
Indication of channel locking to certain video payload
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