Measurement Computing PC-CARD-DAC08 User Manual page 11

S3 S2 S1 S0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 X X X
S3: Setting the S3 bit to 1 enables simultaneous update mode. Setting S3 to 0
updates the DACs in pairs.
Note that DACs are always updated in pairs if S3 is set to 0. For example, if you latch
new data to DAC1, then update the DAC0 and DAC1 pair, DAC1 updates with the
new value and DAC0 updates with the same value as before since the latch (data for
output) has not changed.
If S3 is set to 1, a read from the base +0 register will simultaneously update all eight
DACs with the data previously latched to the DAC registers.
CLR: Setting the CLR bit to 1 resets all eight DAC outputs to 0V. Default and
normal operation is CLR = 0, which has no effect on the DAC outputs.
BASE + 3 - Digital I/O (8 bits)
7 6
DIO7 DIO6
WRITE: Updates output of DIO bits set for output.
READ: Reads current status of DIO bits for input. Reads back output state of DIO
bits set for output.
BASE + 4 - Interrupt Control & Digital I/O Direction Control
7 6
X X
WRITE: Set control bits.
READ: Read status of control bits.
INTREQ Default is no interrupt has occurred = 0. When set to 1 an interrupt has
occurred.
External interrupts, when enabled, occur at TTL falling edge.
A read of base + 1 clears this bit.
Table 5-1. DAC Selection and Update Mode
Function on
Base + 0 Read
Update DAC0 & 1
Update DAC0 & 1
Update DAC2 & 3
Update DAC2 & 3
Update DAC4 & 5
Update DAC4 & 5
Update DAC6 & 7
Update DAC6 & 7
Update All DACs
5 4
DIO5 DIO4
5 4
X X
Function on Base + 0,
Base + 1 Write
Latch new D/A Value for DAC0
Latch new D/A Value for DAC1
Latch new D/A Value for DAC2
Latch new D/A Value for DAC3
Latch new D/A Value for DAC4
Latch new D/A Value for DAC5
Latch new D/A Value for DAC6
Latch new D/A Value for DAC7
No write function if S3 set
3 2
DIO3 DIO2
3 2
INTREQ INT_EN
7
1 0
DIO1 DIO0
1 0
UDIR LDIR