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SONIX SN32F107 User Manual

Sn32f100 series 32-bit cortex-m0 micro-controller
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SN32F100 Series
USER'S MANUAL
SN32F107
SN32F108
SN32F109
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SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.
SONiX TECHNOLOGY CO., LTD
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SN32F100 Series
32-Bit Cortex-M0 Micro-Controller
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Version 1.9

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Summary of Contents for SONIX SN32F107

  • Page 1 SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur.

  • Page 2: Amendent History

    2. Remove SYSTICKPRE[1:0] 3. Remove SYS0_ANTIEFT register. 4. Update WDTPRE[2:0] bits description in SYS1_APBCP1 register. 5. Update TO[15:0] bits description in I2Cn_TOCTRL register. 6. Add Note for setting the pins which are not pin-out. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 2...

  • Page 3: Table Of Contents

    CODE OPTION TABLE ........................35 CORE REGISTER OVERVIEW ..................... 36 SYSTEM CONTROL..........................37 RESET .............................. 37 3.1.1 POWER-ON RESET (POR) ...................... 37 3.1.2 WATCHDOG RESET (WDT RESET) ..................38 3.1.3 BROWN-OUT RESET....................... 38 Version 1.9 SONiX TECHNOLOGY CO., LTD Page 3...
  • Page 4 SYSTEM CONTROL REGISTERS 1 ....................56 3.4.1 AHB Clock Enable register (SYS1_AHBCLKEN) ..............56 3.4.2 APB Clock Prescale register 0 (SYS1_APBCP0) ..............57 3.4.3 APB Clock Prescale register 1 (SYS1_APBCP1) ..............58 Version 1.9 SONiX TECHNOLOGY CO., LTD Page 4...
  • Page 5 GPIO Port n Bits Clear Operation register (GPIOn_BCLR) (n=0,1,2,3) ....... 71 5.3.12 GPIO Port n Open-Drain Control register (GPIOn_ODCTRL) (n=0,1,2,3) ......71 16-BIT TIMER WITH CAPTURE FUNCTION ................74 OVERVIEW ............................. 74 FEATURES ............................74 Version 1.9 SONiX TECHNOLOGY CO., LTD Page 5...
  • Page 6 CT32Bn External Match register (CT32Bn_EM) (n=0,1) ............90 7.7.11 CT32Bn PWM Control register (CT32Bn_PWMCTRL) (n=0,1) ..........90 7.7.12 CT32Bn Timer Raw Interrupt Status register (CT32Bn_RIS) (n=0,1) ........91 7.7.13 CT32Bn Timer Interrupt Clear register (CT32Bn_IC) (n=0,1) ..........91 Version 1.9 SONiX TECHNOLOGY CO., LTD Page 6...
  • Page 7 10.4 INTERFACE DESCRIPTION ....................... 104 10.4.1 SPI ............................104 10.4.2 SSI ............................105 10.4.3 COMMUNICATION FLOW ....................105 10.4.3.1 SINGLE-FRAME ......................105 10.4.3.2 MULTI-FRAME ......................106 10.5 -SEL (A -CS) ........................106 Version 1.9 SONiX TECHNOLOGY CO., LTD Page 7...
  • Page 8 I2C n Timeout Control register (I2Cn_TOCTRL) (n=0,1) ............ 119 11.8.10 I2C n Monitor Mode Control register (I2Cn_MMCTRL) (n=0,1) ........119 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER (UART) ....121 12.1 OVERVIEW ........................... 121 Version 1.9 SONiX TECHNOLOGY CO., LTD Page 8...
  • Page 9 I2S CLCOK CONTROL ......................137 13.4.2 I2S BLOCK DIAGRAM ......................137 13.4.3 16-Bit Sigma-Delta ADC BLOCK DIAGRAM ............... 138 13.4.4 16-Bit Sigma-Delta DAC BLOCK DIAGRAM ............... 139 13.5 FUNCTIONAL DESCRIPTION ....................140 Version 1.9 SONiX TECHNOLOGY CO., LTD Page 9...
  • Page 10 ADC Setting 23 register (ADC_SET23) ................151 13.7.23 ADC Setting 24 register (ADC_SET24) ................152 13.8 CODEC DAC REGISTERS ......................152 13.8.1 DAC Setting 1 register (DAC_SET1) ..................152 13.8.2 DAC Setting 2 register (DAC_SET2) ..................152 Version 1.9 SONiX TECHNOLOGY CO., LTD Page 10...
  • Page 11 PAGE ERASE ........................ 163 15.8.3.2 MASS ERASE ........................ 163 15.9 READ PROTECTION ........................163 15.10 FMC REGISTERS ........................164 15.10.1 Flash Status register (FLASH_STATUS) ................164 15.10.2 Flash Control register (FLASH_CTRL) ................164 Version 1.9 SONiX TECHNOLOGY CO., LTD Page 11...
  • Page 12 LQFP 64 PIN ..........................180 20.3 LQFP 80 PIN ..........................181 MARKING DEFINITION ....................... 182 21.1 INTRODUCTION .......................... 182 21.2 MARKING INDETIFICATION SYSTEM ..................182 21.3 MARKING EXAMPLE ......................... 183 21.4 DATECODE SYSTEM ........................183 Version 1.9 SONiX TECHNOLOGY CO., LTD Page 12...

  • Page 13: Product Overview

    Normal, Sleep, Deep-sleep, and Deep power-down external high/low clock.   Package (Chip form support) Serial Wire Debug (SWD) LQFP 80 pin  In-System Programming (ISP) supported LQFP 64 pin LQFP 48 pin Version 1.9 SONiX TECHNOLOGY CO., LTD Page 13...
  • Page 14 Package Loader MHz) Wakeup 16-bit x 2 SN32F107F 64KB LQFP48 32-bit x 2 16-bit x 2 SN32F108F 64KB LQFP64 32-bit x 2 16-bit x 2 SN32F109F 64KB LQFP80 32-bit x 2 Version 1.9 SONiX TECHNOLOGY CO., LTD Page 14...

  • Page 15: System Block Diagram

    32-bit TIMER 1 I2C0 CT32B1_PWM[1:0] SDA0 with 2 PWM CT32B1_CAP0 SCL1 16-bit TIMER 0 I2C1 CT16B0_PWM[0] SDA1 with 1 PWM CT16B0_CAP0 I2SBCLK I2SWS 16-bit TIMER 1 CT16B1_PWM[0] I2SDIN with 1 PWM CT16B1_CAP0 I2SDOUT I2SMCLK Version 1.9 SONiX TECHNOLOGY CO., LTD Page 15...

  • Page 16: Clock Generation Block Diagram

    SSP1CLKEN DACCLKEN clock source register block /1,2,4,8,16 AHB clock for AHB clock for ADC Comparator Comparator CMP_PCLK Comparator Comparator Clock Prescaler clock source register block register block clock source CMPCLKEN /1,2,4,8,16 ADCCLKEN Version 1.9 SONiX TECHNOLOGY CO., LTD Page 16...

  • Page 17: Pin Assignment

    P0.13/SWDIO 18 43 P1.10/LXTALIN P0.14/DPDWAKEUP 19 42 VSS P0.15/RESET 20 41 VDD 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Version 1.9 SONiX TECHNOLOGY CO., LTD Page 17...
  • Page 18 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32  Note: The pins which are not pin-out shall be set correctly to decrease power consumption in low- power modes. Strongly recommended to set these pins as input pull-up. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 18...
  • Page 19 13 14 15 16 17 18 19 20 21 22 23 24  Note: The pins which are not pin-out shall be set correctly to decrease power consumption in low- power modes. Strongly recommended to set these pins as input pull-up. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 19...

  • Page 20: Pin Descriptions

    P0.7 — General purpose digital input/output pin with high-current sink driver. P0.7/MOSI0 MOSI0 — Master Out Slave In for SSP0. P0.8 — General purpose digital input/output pin. P0.8/SCK1 SCK1 — Serial clock for SSP1. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 20...
  • Page 21 P1.7 — General purpose digital input/output pin. P1.7/MIC_P MIC_P — Sigma-delta ADC MIC difference input (+). P1.8 — General purpose digital input/output pin. P1.8/MIC_N MIC_N — Sigma-delta ADC MIC difference input (-). Version 1.9 SONiX TECHNOLOGY CO., LTD Page 21...
  • Page 22 P2.7/CM7 CM7 — Comparator channel 7. P2.8 — General purpose digital input/output pin. P2.8/CM8 CM8 — Comparator channel 8. P2.9 — General purpose digital input/output pin. P2.9/CM9 CM9 — Comparator channel 9. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 22...
  • Page 23 CT32B0_PWM1 — PWM output 1 for CT32B0. P3.7 — General purpose digital input/output pin. P3.7/CM23/ CM23 — Comparator channel 23. CT32B1_PWM1 CT32B1_PWM1 — PWM output 1 for CT32B1. P3.8 — General purpose digital input/output pin. P3.8/CMO Version 1.9 SONiX TECHNOLOGY CO., LTD Page 23...
  • Page 24 CT32B0_CAP0 — Capture input 0 for CT32B0. P3.15 — General purpose digital input/output pin with high-current sink driver. P3.15/SDA1/ SDA1 — I2C data input/output. CT32B1_CAP0 CT32B1_CAP0 — Capture input 0 for CT32B1. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 24...

  • Page 25: Pin Circuit Diagrams

    GPIOn_CFG GPIOPn_MODE Output Bus Output Latch Specific Output Bus *. Specific Output Function Control Bit Specific Input Function Control Bit *. Some specific functions switch I/O direction directly, not through GPIOn_MODE register. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 25...
  • Page 26 I/O Input Bus GPIOn_CFG GPIOPn_MODE Output I/O Output Bus Latch Analog IP Output Terminal *. Specific Output Function Control Bit *. Some specific functions switch I/O direction directly, not through GPIOn_MODE register. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 26...

  • Page 27: Central Processor Unit (Cpu)

    0x4001 6000 Reserved Reserved 0x4001 4000 0x4001 2000 0x0001 0000 0x4001 0000 Reserved 64 KB on-chip FLASH 0x4000 8000 CT32B1 0x4000 6000 0x0000 0000 CT32B0 0x4000 4000 CT16B1 0x4000 2000 CT16B0 0x4000 0000 Version 1.9 SONiX TECHNOLOGY CO., LTD Page 27...

  • Page 28: System Tick Timer

    When the counter transitions to zero, the COUNTFLAG status bit is set to 1. The COUNTFLAG bit clears on reads.  Note: When the processor is halted for debugging the counter does not decrease. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 28...

  • Page 29: Systick Usage Hints And Tips

    RELOAD = (system tick clock frequency × 10 ms) −1 = (50 MHz × 10 ms) −1 = 0x0007A11F. Name Description Attribute Reset 31:24 Reserved Value to load into the SYST_CVR when the counter is enabled and when 23:0 RELOAD 0x5F7F9B it reaches 0. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 29...

  • Page 30: System Tick Timer Current Value Register (Systick_Val)

    1: TENMS value is inexact, or not given. 29:24 Reserved Reload value for 10ms timing, subject to system clock skew errors. If the 23:0 TENMS 0xA71FF value reads as zero, the calibration value is not known. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 30...

  • Page 31: Nested Vectored Interrupt Controller (Nvic)

    CT32B0 0x0000 0090 Settable IRQ21/CT32B1IRQ CT32B1 0x0000 0094 Settable IRQ22/I2SIRQ 0x0000 0098 Settable IRQ23/SSP0IRQ SSP0 0x0000 009C Settable IRQ24/SSP1IRQ SSP1 0x0000 00A0 Settable IRQ25/UART0IRQ UART0 0x0000 00A4 Settable IRQ26/UART1IRQ UART1 0x0000 00A8 Version 1.9 SONiX TECHNOLOGY CO., LTD Page 31...

  • Page 32: Irq0~31 Interrupt Set-Enable Register (Nvic_Iser)

    The ICPR removes the pending state from interrupts, and shows the interrupts that are pending. Note: Writing 1 to an ICPR bit does not affect the active state of the corresponding interrupt. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 32...

  • Page 33: Irq0~31 Interrupt Priority Register (Nvic_Iprn) (N=0~7)

    1: Requests a system level reset. Reserved for debug use. This bit read as 0. When writing to the register VECTCLRACTIVE you must write 0 to this bit, otherwise behavior is Unpredictable. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 33...
  • Page 34 SN32F100 Series 32-Bit Cortex-M0 Micro-Controller Reserved Version 1.9 SONiX TECHNOLOGY CO., LTD Page 34...

  • Page 35: Code Option Table

    32-Bit Cortex-M0 Micro-Controller 2.5 CODE OPTION TABLE Address: 0x1FFF 2000 Name Description Attribute Reset 31:16 Code Security[15:0] Code Security 0xFFFF 0xFFFF: CS0 0x5A5A: CS1 0xA5A5: CS2 0x55AA: CS3 15:4 Reserved Reserved Reserved Version 1.9 SONiX TECHNOLOGY CO., LTD Page 35...

  • Page 36: Core Register Overview

    These registers are mutually exclusive bit fields in the 32-bit PSR. The PRIMASK register prevents activation of all exceptions with configurable priority. PRIMASK CONTROL The CONTROL register controls the stack used when the processor is in Thread mode. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 36...

  • Page 37: System Control

    System initialization: All system registers is set as initial conditions and system is ready.  Oscillator warm up: Oscillator operation is successfully and supply to system clock.  Program executing: Power on sequence is finished and program executes from Boot loader. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 37...

  • Page 38: Watchdog Reset (Wdt Reset)

    The power source of DC application is usually using battery. When low battery condition and MCU drive any loading, the power drops and keeps in dead-band. Under the situation, the power won’t drop deeper and not touch the system reset voltage. That makes the system under dead-band. AC application: Version 1.9 SONiX TECHNOLOGY CO., LTD Page 38...

  • Page 39: The System Operating Voltage Decsription

    External reset circuit. (Zener diode reset circuit, Voltage bias reset circuit, External reset IC)  Note: The “Zener diode reset circuit”, “Voltage bias reset circuit” and “External reset IC” can completely improve the brown out reset, DC low battery and AC slow power down conditions. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 39...

  • Page 40: External Reset

    Delay Time The LVD (low voltage detector) is built-in SONiX 32-bit MCU to be brown out reset protection. When the VDD drops and is below LVD detect voltage, the LVD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt;...

  • Page 41: Simply Rc Reset Circuit

    The reset circuit has a simply protection against unusual power. The diode offers a power positive path to conduct higher power to VDD. It is can make reset pin voltage level to synchronize with VDD voltage. The structure can improve slight brown out reset condition. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 41...

  • Page 42: Zener Diode Reset Circuit

    VDD voltage level is above or equal to “0.7V x (R1 + R2) / R1”, the C terminal of the PNP transistor outputs high voltage and MCU operates normally. When VDD is below “0.7V x (R1 + R2) / R1”, the C terminal of the PNP transistor Version 1.9 SONiX TECHNOLOGY CO., LTD Page 42...

  • Page 43: External Reset Ic

    The internal reset is deasserted and the MCU loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 43...

  • Page 44: System Clock

    RC type oscillator circuit. The frequency is affected by the voltage and temperature of the system. In common condition, the frequency of the RC oscillator is about 16 KHz.  Note: The ILRC can ONLY be switched on and off by HW. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 44...

  • Page 45: Pll

    5. P = 6, 8, 10, 12, or 14 (duty 50% +/- 2.5%) 6. F = 20MHz, 30MHz, 40MHz, 50MHz, 24MHz, 36MHz, 48MHz, 32MHz, 22MHz, 24MHz, 50MHz CLKOUT with jitter < ±500 ps Version 1.9 SONiX TECHNOLOGY CO., LTD Page 45...

  • Page 46: External Clock Source

    Main Purpose: System high clock source, RTC clock source, and PLL clock source.  Warm-up Time: 2048*F  XIN/XOUT Shared Pin Selection: Oscillator Mode XTALIN pin XTALOUT pin GPIO IHRC GPIO Crystal/Ceramic Crystal/Ceramic EHS X’TAL Version 1.9 SONiX TECHNOLOGY CO., LTD Page 46...

  • Page 47: Audio External High-Speed (Auehs) Clock

    Crystal devices are driven by LXIN, LXOUT pins. The 32768 crystal and 10pF capacitor must be as near as possible to MCU. The ELS crystal is switched on and off using the ELSEN bit in Analog Block Control register (SYS0_ANBCTRL). Version 1.9 SONiX TECHNOLOGY CO., LTD Page 47...

  • Page 48: Bypass Mode

    The 1 to 25 MHz EHS X’TAL has the advantage of producing a very accurate rate External X’TAL on the main clock (EHS/ELS X’TAL) ELS X’TAL must have a frequency of 32.768 KHz. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 48...

  • Page 49: System Clock (Sysclk) Selection

    One of 6 clock signals can be selected as clock output: HCLK IHRC ILRC PLL clock output ELS X’TAL EHS X’TAL AUEHS X’TAL The selection is controlled by the CLKOUTSEL bits in SYS1_AHBCLKEN register. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 49...

  • Page 50: System Control Registers 0

    Note: PLLEN bit can NOT be cleared if the PLL is selected as system clock or is selected to become the system clock. Name Description Attribute Reset 31:16 Reserved PLL enable PLLEN 0: Disable 1: Enable Reserved Version 1.9 SONiX TECHNOLOGY CO., LTD Page 50...

  • Page 51: Recommend Frequency Setting

    44MHz 48MHz 50MHz Fclkin 10MHz 12MHz 16MHz 22MHz 24MHz 25MHz 3.3.2.1 RECOMMEND FREQUENCY SETTING / F * M CLKIN CLKOUT (MHz) (MHz) FSEL MSEL[4:0]=M PSEL[2:0] P= PSEL[2:0]*2 (MHz) CLKIN CLKOUT /F*M CLKIN Version 1.9 SONiX TECHNOLOGY CO., LTD Page 51...

  • Page 52: Clock Source Status Register (Sys0_Csst)

    Set and cleared by SW. 000: IHRC 001: ILRC 010: EHS X’TAL 011: ELS X’TAL 100: PLL output Other: Reserved 3.3.5 AHB Clock Prescale register (SYS0_AHBCP) Address Offset: 0x10 Name Description Attribute Reset 31:4 Reserved Version 1.9 SONiX TECHNOLOGY CO., LTD Page 52...

  • Page 53: System Reset Status Register (Sys0_Rstst)

    The LVD control register selects four separate threshold values for generating a LVD interrupt to the NVIC or LVD reset. Name Description Attribute Reset 31:16 Reserved LVD enable LVDEN 0: Disable 1: Enable LVD Reset enable LVDRSTEN 0: Disable 1: Enable Version 1.9 SONiX TECHNOLOGY CO., LTD Page 53...
  • Page 54 11: The interrupt assertion threshold voltage is 3.00V Reserved LVD reset level LVDRSTLVL[1:0] 00: The reset assertion threshold voltage is 2.00V 01: The reset assertion threshold voltage is 2.40V 10: The reset assertion threshold voltage is 2.70V 11: Reserved Version 1.9 SONiX TECHNOLOGY CO., LTD Page 54...

  • Page 55: External Reset Pin Control Register (Sys0_Exrstctrl)

    Attribute Reset 31:1 Reserved SWD pin disable bit. SWDDIS 0: Enable SWD pin. (P0.13 acts as SWDIO pin, P0.12 acts as SWCLK pin) 1: Disable. (P0.13 and P0.12 act as GPIO pins) Version 1.9 SONiX TECHNOLOGY CO., LTD Page 55...

  • Page 56: System Control Registers 1

    0: Disable 1: Enable 15:14 Reserved Enables clock for SSP1. SSP1CLKEN 0: Disable 1: Enable Enables clock for SSP0. SSP0CLKEN 0: Disable 1: Enable Enables clock for Comparator. CMPCLKEN 0: Disable 1: Enable Version 1.9 SONiX TECHNOLOGY CO., LTD Page 56...

  • Page 57: Apb Clock Prescale Register 0 (Sys1_Apbcp0)

    Other: Reserved Reserved Comparator clock source prescale value 18:16 CMPPRE[2:0] 000: HCLK / 1 001: HCLK / 2 010: HCLK / 4 011: HCLK / 8 100: HCLK / 16 Other: Reserved Reserved Version 1.9 SONiX TECHNOLOGY CO., LTD Page 57...

  • Page 58: Apb Clock Prescale Register 1 (Sys1_Apbcp1)

    Other: Reserved Reserved I2C1 clock source prescale value 26:24 I2C1PRE[2:0] 000: HCLK / 1 001: HCLK / 2 010: HCLK / 4 011: HCLK / 8 100: HCLK / 16 Other: Reserved Reserved Version 1.9 SONiX TECHNOLOGY CO., LTD Page 58...

  • Page 59: Peripheral Reset Register (Sys1_Prst)

    0: No effect 1: Reset Codec DAC WDT reset WDTRST 0: No effect 1: Reset WDT RTC reset RTCRST 0: No effect 1: Reset RTC I2S reset I2SRST 0: No effect 1: Reset I2S Version 1.9 SONiX TECHNOLOGY CO., LTD Page 59...
  • Page 60 0: No effect 1: Reset GPIO port 2 GPIO port 1 reset GPIOP1RST 0: No effect 1: Reset GPIO port 1 GPIO port 0 reset GPIOP0RST 0: No effect 1: Reset GPIO port 0 Version 1.9 SONiX TECHNOLOGY CO., LTD Page 60...

  • Page 61: System Operation Mode

    Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. The power state of the analog blocks (IHRC, EHS X’TAL, ELS X’TAL, PLL, Flash, LVD, Codec, Comparator) is Version 1.9 SONiX TECHNOLOGY CO., LTD Page 61...

  • Page 62: Deep-Sleep Mode

    Wakes up the chip from Deep power-down mode by pulling the DPDWAKEUP pin LOW (Turn on the on-chip voltage regulator. When the core voltage reaches the power-on-reset (POR) trip point, a system reset will be triggered and the chip re-boots). The RESET pin has no functionality in Deep power-down mode. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 62...

  • Page 63: Entering Deep Power-Down Mode

    Sleep mode, MCU waits for 2048 external high-speed oscillator clocks and 32 internal high-speed oscillator clocks as the wakeup time to stable the oscillator circuit. After the wakeup time, the system goes into the normal mode. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 63...

  • Page 64: State Machine Of Pmu

    Wake-up condition Interrupt Wake-up condition GPIO Wakeup Enter mode condition RTC interrupt 1. DSLEEPEN = 1 2. WFI instruction Reset condition One of reset trigger sources actives Deep-sleep mode Version 1.9 SONiX TECHNOLOGY CO., LTD Page 64...

  • Page 65: Operation Mode Comparsion Table

    By RTCEN Peripherals By Enable bit of each peripherals Disable HCLK GPIO interrupt, All interrupts, Wakeup Source RTC interrupt, DPDWAKEUP pin RESET pin RESET pin RTCENB RTC_CLKS ILRC* ELS* 0 (ILRC) 1 (ELS) Version 1.9 SONiX TECHNOLOGY CO., LTD Page 65...

  • Page 66: Pmu Registers

    Deep sleep mode enable DSLEEPEN 0: Disable. 1: Enable. WFI instruction will make MCU enter Deep-sleep mode. Deep power-down mode enable DPDEN 0: Disable. 1: Enable. WFI instruction will make MCU enter Deep power-down mode. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 66...

  • Page 67: General Purpose I/O Port (Gpio)

    Note: HW will switch P1.7 and P1.8 to Microphone differential input if SEL_MIC=1 in ADC_SET23 register. Setting SEL_MIC=0 before P1.7 and P1.8 as GPIO function.  Note: P0.14 is the input pin only, please don’t set it to the output function in GPIO0_MODE register. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 67...

  • Page 68: Gpio Registers

    31:30 CFG15[1:0] 00: Pull-up resistor enabled. 01: Pull-down resistor enabled. 10: Inactive (no pull-down/pull-up resistor enabled). 11: Repeater mode. Configuration of Pn.14 29:28 CFG14[1:0] 00: Pull-up resistor enabled. 01: Pull-down resistor enabled. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 68...
  • Page 69 10: Inactive (no pull-down/pull-up resistor enabled). 11: Repeater mode. Configuration of Pn.1 CFG1[1:0] 00: Pull-up resistor enabled. 01: Pull-down resistor enabled. 10: Inactive (no pull-down/pull-up resistor enabled). 11: Repeater mode. Configuration of Pn.0 CFG0[1:0] Version 1.9 SONiX TECHNOLOGY CO., LTD Page 69...

  • Page 70: Gpio Port N Interrupt Sense Register (Gpion_Is) (N=0,1,2,3)

    Name Description Attribute Reset 31:16 Reserved Selects interrupt on pin x to be enabled (x = 0 to 15). 15:0 IE[15:0] 0: Disable Interrupt on Pn.x 1: Enable Interrupt on Pn.x Version 1.9 SONiX TECHNOLOGY CO., LTD Page 70...

  • Page 71: Gpio Port N Raw Interrupt Status Register (Gpion_Ris) (N=0,1,2,3)

    5.3.12 GPIO Port n Open-Drain Control register (GPIOn_ODCTRL) (n=0,1,2,3) Address offset: 0x2C Several I/Os have built-in open-drain function and must be set as output mode when enable open-drain function. Open-drain external circuit is as following. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 71...
  • Page 72 1: Enable. HW set P0.2 as output mode automatically. n=1~3 Reserved n = 0 Pn1OC P0.1 open-drain control bit. 0: Disable 1: Enable. HW set P0.1 as output mode automatically. n=1~3 Reserved Version 1.9 SONiX TECHNOLOGY CO., LTD Page 72...
  • Page 73 SN32F100 Series 32-Bit Cortex-M0 Micro-Controller n = 0 Pn0OC P0.0 open-drain control bit. 0: Disable 1: Enable. HW set P0.0 as output mode automatically. n=1~3 Reserved Version 1.9 SONiX TECHNOLOGY CO., LTD Page 73...

  • Page 74: 16-Bit Timer With Capture Function

    – Toggle on match. – Do nothing on match. PIN DESCRIPTION Pin Name Type Description GPIO Configuration CT16Bn_CAP0 Capture channel input 0 Depends on GPIOn_CFG CT16Bn_PWMx Output channel x of Match/PWM output. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 74...

  • Page 75: Block Diagram

    SN32F100 Series 32-Bit Cortex-M0 Micro-Controller BLOCK DIAGRAM MRxSTOP CRST CRST MRxIF STOP STOP MRxIE MRx Interrupt PCLK MRxRST RESET RESET PWMxEN CT16Bn_PWMx PWMxIOEN EMCx CAP0 CAP0EN CT16Bn_CAP0 CAP0FE CAP0IE CAP0 Interrupt CAP0RE Version 1.9 SONiX TECHNOLOGY CO., LTD Page 75...

  • Page 76: Timer Operation

    6. After the timer reaches the match value, the CEN bit in CT16Bn_TMRCTRL register is cleared, and the interrupt indicating that a match occurred is generated. PCLK CT16Bn_PC CT16Bn_TC CEN bit Interrupt Version 1.9 SONiX TECHNOLOGY CO., LTD Page 76...

  • Page 77: Pwm

    PWM cycle length. For this register, set the MRnR bit to one to enable the timer reset when the timer value matches the value of the corresponding match register. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 77...

  • Page 78: Ct16B Nregisters

    Register, the Timer Counter is incremented, and the Prescale Counter is reset on the next PCLK. This causes the TC to increment on every PCLK when PR = 0, every 2 PCLKs when PR = 1, etc. Name Description Attribute Reset Version 1.9 SONiX TECHNOLOGY CO., LTD Page 78...

  • Page 79: Ct16Bn Count Control Register (Ct16Bn_Cntctrl) (N=0,1)

    0: Disable 1: Enable Enable reset TC when MR3 matches TC. MR3RST 0: Disable 1: Enable Enable generating an interrupt when MR3 matches the value in the TC. MR3IE 0: Disable 1: Enable Version 1.9 SONiX TECHNOLOGY CO., LTD Page 79...

  • Page 80: Ct16Bn Match Register 0~3 (Ct16Bn_Mr0~3) (N=0,1)

    Note: HW will switch I/O Configuration directly when CAP0EN=1. Name Description Attribute Reset 31:7 Reserved Capture 0 function enable bit CAP0EN 0: Disable 1: Enable Capture 0 function for external Capture pin. 2~3: Reserved. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 80...

  • Page 81: Ct16Bn Capture 0 Register (Ct16Bn_Cap0) (N=0,1)

    PWM output is set to HIGH. The timer is reset by the match register that is configured to set the PWM cycle length. When the timer is reset to zero, all currently HIGH match outputs configured as PWM outputs are cleared. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 81...

  • Page 82: Ct16Bn Timer Raw Interrupt Status Register (Ct16Bn_Ris) (N=0,1)

    0: No effect MR3IC 1: Clear MR3IF bit 0: No effect MR2IC 1: Clear MR2IF bit 0: No effect MR1IC 1: Clear MR1IF bit 0: No effect MR0IC 1: Clear MR0IF bit Version 1.9 SONiX TECHNOLOGY CO., LTD Page 82...

  • Page 83: 32-Bit Timer With Capture Function

    – Toggle on match. – Do nothing on match. 7.3 PIN DESCRIPTION Pin Name Type Description GPIO Configuration CT32Bn_CAP0 Capture channel input 0 Depends on GPIOn_CFG CT32Bn_PWMx Output channel x of Match/PWM output. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 83...

  • Page 84: Block Diagram

    SN32F100 Series 32-Bit Cortex-M0 Micro-Controller 7.4 BLOCK DIAGRAM MRxSTOP CRST CRST MRxIF STOP STOP MRxIE MRx Interrupt PCLK MRxRST RESET RESET PWMxEN CT32Bn_PWMx PWMxIOEN EMCx CAP0 CAP0EN CT32Bn_CAP0 CAP0FE CAP0IE CAP0 Interrupt CAP0RE Version 1.9 SONiX TECHNOLOGY CO., LTD Page 84...

  • Page 85: Timer Operation

    6. In the next clock after the timer reaches the match value, the CEN bit in CT32Bn_TMRCTRL register is cleared, and the interrupt indicating that a match occurred is generated. PCLK CT32Bn_PC CT32Bn_TC CEN bit Interrupt Version 1.9 SONiX TECHNOLOGY CO., LTD Page 85...

  • Page 86: Pwm

    PWM cycle length. For this register, set the MRnR bit to one to enable the timer reset when the timer value matches the value of the corresponding match register. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 86...

  • Page 87: Ct32B Nregisters

    Register, the Timer Counter is incremented, and the Prescale Counter is reset on the next PCLK. This causes the TC to increment on every PCLK when PR = 0, every 2 PCLKs when PR = 1, etc. Name Description Attribute Reset 31:0 PC[31:0] Prescale Counter Version 1.9 SONiX TECHNOLOGY CO., LTD Page 87...

  • Page 88: Ct32Bn Count Control Register (Ct32Bn_Cntctrl) (N=0,1)

    Stop MR2: TC and PC will stop and CEN bit will be cleared if MR2 MR2STOP matches TC. 0: Disable 1: Enable Enable reset TC when MR2 matches TC. MR2RST 0: Disable 1: Enable Version 1.9 SONiX TECHNOLOGY CO., LTD Page 88...

  • Page 89: Ct32Bn Match Register 0~3 (Ct32Bn_Mr0~3) (N=0,1)

    1: Enable a sequence of 1 then 0 on CT32Bn_CAP0 signal will cause CAP0 to be loaded with the contents of TC. 2: Enable a sequence of 1 then 0 on CT32Bn_CAP0 signal will reset the 3: Reserved. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 89...

  • Page 90: Ct32Bn Capture 0 Register (Ct32Bn_Cap0) (N=0,1)

    PWM cycle length. When the timer is reset to zero, all currently HIGH match outputs configured as PWM outputs are cleared. Name Description Attribute Reset 31:22 Reserved CT32Bn_PWM1/GPIO selection bit PWM1IOEN Version 1.9 SONiX TECHNOLOGY CO., LTD Page 90...

  • Page 91: Ct32Bn Timer Raw Interrupt Status Register (Ct32Bn_Ris) (N=0,1)

    0: No effect MR3IC 1: Clear MR3IF bit 0: No effect MR2IC 1: Clear MR2IF bit 0: No effect MR1IC 1: Clear MR1IF bit 0: No effect MR0IC 1: Clear MR0IF bit Version 1.9 SONiX TECHNOLOGY CO., LTD Page 91...

  • Page 92: Watchdog Timer (Wdt)

    The clock to the watchdog register block can be disabled in AHB Clock Enable register (SYS1_AHBCLKEN) register for power savings. Watchdog reset or interrupt will occur any time the watchdog is running and has an operating clock source. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 92...

  • Page 93: Block Diagram

    SN32F100 Series 32-Bit Cortex-M0 Micro-Controller BLOCK DIAGRAM Feed Watchdog WDT_TC WDT_FEED Feed OK Reload Counter WDT_PCLK /128 8-bit Down Counter Enable Counter underflow WDT_CFG WDINT WDTIE WDTEN WDT Reset WDT Interrupt Version 1.9 SONiX TECHNOLOGY CO., LTD Page 93...

  • Page 94: Wdt Registers

    Name Description Attribute Reset Watchdog register key. 31:16 WDKEY Read as 0. When writing to the register you must write 0x5AFA to WDKEY, otherwise behavior of writing to the register is ignored. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 94...

  • Page 95: Watchdog Feed Register (Wdt_Feed)

    WDKEY, otherwise behavior of writing to the register is ignored. Feed value (Read as 0x0) 15:0 FV[15:0] 0x55AA: The watchdog is fed, and the WDT_TC value is reloaded in the watchdog counter. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 95...

  • Page 96: Real-Time Clock (Rtc)

    The RTC Overflow interrupt flag (OVFIF) is asserted on the last RTC Core clock cycle before the counter reaches 0x0. The RTC Alarm interrupt flag (ALMIF) are asserted on the last RTC Core clock cycle before the counter reaches the RTC Alarm counter reload value stored in the Alarm register. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 96...

  • Page 97: Rtc Operation

    The following figure shows the RTC waveform when it is configured with RTC_SECCNTV=3, RTC_ALMCNTV=0x1000. …… RTC_PCLK …… RTC_SECCNT Cleared by SW …… RTC_SECIF …… RTC_ALMCNT 0x9FF 0x1000 0x1001 …… RTC_ALMIF RTC_PCLK RTC_SECCNT RTC_ALMCNT 0xFFFFFFFD 0xFFFFFFFE 0xFFFFFFFF Cleared by SW RTC_OVFIF Version 1.9 SONiX TECHNOLOGY CO., LTD Page 97...

  • Page 98: Block Diagram

    SN32F100 Series 32-Bit Cortex-M0 Micro-Controller 9.4 BLOCK DIAGRAM EHS_XTAL/128 ELS_XTAL SRC_SEL ILRC CLKSEL RTCEN SECIE SEC_CNT_CLK SECOND Interrupt RTC_SECCNTV RTC_SECCNT SECOND ALMIE ALARM Interrupt RTC_ALMCNTV RTC_ALMCNT OVERFLOW Interrupt OVFIE Version 1.9 SONiX TECHNOLOGY CO., LTD Page 98...

  • Page 99: Rtc Registers

    OVFIF This bit is set by HW when ALM_CNT overflows (ALM_CNT counts from 0xFFFFFFFF to 0x0). An interrupt is generated if OVFIE=1. 0: Overflow not detected 1: 32-bit programmable counter overflow occurred. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 99...

  • Page 100: Rtc Interrupt Clear Register (Rtc_Ic)

    Attribute Reset 31:0 ALMCNTV[31:0] 0xFFFFFFFF RTC alarm counter reload value. Update this register will reset ALMCNT. The zero value is not recommended, and will be replaced with default value (0xFFFFFFFF) by HW. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 100...

  • Page 101: Rtc Alarm Count Register (Rtc_Almcnt)

    SN32F100 Series 32-Bit Cortex-M0 Micro-Controller 9.5.9 RTC Alarm Count register (RTC_ALMCNT) Address offset: 0x20 Name Description Attribute Reset RTC alarm counter 31:0 ALMCNT[31:0] The current value of the RTC alarm counter. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 101...

  • Page 102: Spi/Ssp

    Maximum SPI speed of 25 Mbps (master) or 6 Mbps (slave) in SSP mode.  Data transfer format is from MSB or LSB controlled by register.  The start phase of data sampling location selection is 1 -phase or 2 -phase controlled register. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 102...

  • Page 103: Pin Description

    SSP Slave Select (Slave) Depends on GPIOn_CFG MISOn Master In Slave Out (Master) Depends on GPIOn_CFG Master In Slave Out (Slave) Master Out Slave In (Master) MOSIn Master Out Slave In (Slave) Depends on GPIOn_CFG Version 1.9 SONiX TECHNOLOGY CO., LTD Page 103...

  • Page 104: Interface Description

    The SPI data transfer timing as following figure: MLSB CPOL CPHA Idle Diagrams Status bit1 High bit1 bit1 Next data High bit1 Next data bit1 High bit1 bit1 Next data High bit1 Next data Version 1.9 SONiX TECHNOLOGY CO., LTD Page 104...

  • Page 105: Ssi

    SCK. The received data is transferred from the serial shifter to the receive FIFO on the first rising edge of SCK after the LSB has been latched. 10.4.3 COMMUNICATION FLOW 10.4.3.1 SINGLE-FRAME CPOL=0 CPHA=1 CPOL=1 CPHA=0 CPOL=1 CPHA=1 CPOL=0 CPHA=0 DATA DATA DATA Version 1.9 SONiX TECHNOLOGY CO., LTD Page 105...

  • Page 106: Multi-Frame

    Auto-SEL function is enabled, hardware controls the SEL output, and the actual value of SEL will be copied in the SELCTRL Control bit of the SPI. As long as Auto-SEL is enabled, the value of the SELCTRL Control bit is read-only for software. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 106...

  • Page 107: Ssp Registers

    Slave data output disable bit (ONLY used in slave mode) SDODIS 0: Enable slave data output. 1: Disable slave data output. (MISO=0) Loop back mode enable LOOPBACK 0: Disable 1: Data input from data output Version 1.9 SONiX TECHNOLOGY CO., LTD Page 107...

  • Page 108: Ssp N Control Register 1 (Sspn_Ctrl1) (N=0, 1)

    0: TX FIFO is NOT full. 1: TX FIFO is full. TX FIFO empty flag TX_EMPTY 0: TX FIFO is NOT empty. In Master mode, the transmitter will begin to transmit automatically. 1: TX FIFO is empty. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 108...

  • Page 109: Ssp N Interrupt Enable Register (Sspn_Ie) (N=0, 1)

    10.6.7 SSP n Interrupt Clear register (SSPn_IC) (n=0, 1) Address Offset: 0x18 Name Description Attribute Reset 31:4 Reserved 0: No effect TXFIFOTHIC 1: Clear TXFIFOTHIF bit. 0: No effect RXFIFOTHIC 1: Clear RXFIFOTHIF bit. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 109...

  • Page 110: Ssp N Data Register (Sspn_Data) (N=0, 1)

    10.6.9 SSP n Data Fetch register (SSPn_DF) (n=0, 1) Address Offset: 0x20 Name Description Attribute Reset 31:1 Reserved SSP data fetch control bit 0: Disable 1: Enable when SCKn frequency > 6MHz Version 1.9 SONiX TECHNOLOGY CO., LTD Page 110...

  • Page 111: I2C

     Serial clock synchronization allows devices with different bit rates to communicate via one serial bus.  Serial clock synchronization is used as a handshake mechanism to suspend and resume serial transfer. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 111...

  • Page 112: Pin Description

    I2C Serial clock Output with Open-drain Input depends on GPIOn_CFG SDAn I2C Serial data Output with Open-drain Input depends on GPIOn_CFG 11.4 WAVE CHARACTERISTICS Data Data START STOP Change Change Signal Signal Allowed Allowed Version 1.9 SONiX TECHNOLOGY CO., LTD Page 112...

  • Page 113: I2C Master Modes

    “not acknowledge” to the bus. Arbitration is lost when another device on the bus pulls this signal low. Since this can occur only at the end of a serial byte, the I2C block generates no further clock pulses. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 113...

  • Page 114: I2C Slave Modes

    11.6 I2C SLAVE MODES 11.6.1 SLAVE TRANSMITTER MODE R/W=0 Receiving Address Transmission Data R/W=1 ACK_ ACK_ 11.6.2 SLAVE RECEIVER MODE Receiving Address Receiving Data Receiving Data R/W=0 ACK_ ACK_ ACK_ Terminate by Master Version 1.9 SONiX TECHNOLOGY CO., LTD Page 114...

  • Page 115: Monitor Mode

    Whether any such hardware will be added is still to be determined. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 115...

  • Page 116: I2C Registers

     The address in the Slave Address register has been received.  The General Call address has been received while the General Call bit (GC) in the ADR register is set. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 116...

  • Page 117: I2C N Status Register (I2Cn_Stat) (N=0,1)

    1: MASTER modea STOP condition was issued. SLAVE modea STOP condition was received. NACK done status NACK_STAT 0 : Not received a NACK 1 : Received a NACK ACK done status ACK_STAT 0 : Not received an ACK Version 1.9 SONiX TECHNOLOGY CO., LTD Page 117...

  • Page 118: I2C N Tx Data Register (I2Cn_Txdata) (N=0,1)

    ADD[9:0] is valid when ADD_MODE = 1 ADD[7:1] is valid when ADD_MODE = 0 11.8.7 I2C n SCL High Time register (I2Cn_SCLHT) (n=0,1) Address Offset: 0x20  Note: I2C Bit Frequency = I2Cn_PCLK / (I2Cn_SCLHT+I2Cn_SCLLT) Version 1.9 SONiX TECHNOLOGY CO., LTD Page 118...

  • Page 119: I2C N Scl Low Time Register (I2Cn_Scllt) (N=0,1)

    0: SCL output will be forced high. 1: I2C module may act as a slave peripheral just like in normal operation, the I2C holds the clock line low until it has had time to respond to an I2C Version 1.9 SONiX TECHNOLOGY CO., LTD Page 119...
  • Page 120 SN32F100 Series 32-Bit Cortex-M0 Micro-Controller interrupt. Monitor mode enable bit. MMEN 0: Disable 1: Enable. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 120...

  • Page 121: Universal Asynchronous Receiver And Transmitter (Uart)

    Receiver FIFO trigger points at 1, 4, 8, and 14 bytes.  Built-in baud rate generator.  Software or hardware flow control. 12.3 PIN DESCRIPTION Pin Name Type Description GPIO Configuration UTXDn Serial Transmit data. URXDn Serial Receive data. Depends on GPIOn_CFG Version 1.9 SONiX TECHNOLOGY CO., LTD Page 121...

  • Page 122: Block Diagram

    SN32F100 Series 32-Bit Cortex-M0 Micro-Controller 12.4 BLOCK DIAGRAM UTXD UARTn_TH UART Baud Rate Generator INTERRUPT UARTn_RB URXD UARTn_IE UARTn_II UARTn_FC UARTn_LS UARTn_LC Version 1.9 SONiX TECHNOLOGY CO., LTD Page 122...

  • Page 123: Baud Rate Calculation

    ● OVER8=0: Oversampling by 16 to increase the tolerance of the receiver to clock deviations. In this case, the maximum speed is limited to maximum UARTn_PCLK/16 Sampled values 12 13 15 16 Sampling Clock 6 / 16 7 / 16 7 / 16 1-BIT TIME Version 1.9 SONiX TECHNOLOGY CO., LTD Page 123...

  • Page 124: Auto-Baud Flow

    (ABTOIE bit in UARTn_IE register is set and the auto-baud has completed successfully). The auto-baud interrupts have to be cleared by setting the corresponding ABTOINTCLR and ABEOIE bits in Version 1.9 SONiX TECHNOLOGY CO., LTD Page 124...

  • Page 125: Auto-Baud Modes

    Start bit LSB of “A” or “a” URXD START bit in UARTn_ABCTRL Rate Counter 16 x Baud Rate 16 Cycles 16 Cycles  AUTO-BAUD RATE MODE 1 Waveform Version 1.9 SONiX TECHNOLOGY CO., LTD Page 125...
  • Page 126 “A” (0x41) or “a” (0x61) Start bit7 Parity Stop bit0 bit1 bit2 bit3 bit4 bit5 bit6 Start bit LSB of “A” or “a” URXD START bit in UARTn_ABCTRL Rate Counter 16 x Baud Rate 16 Cycles Version 1.9 SONiX TECHNOLOGY CO., LTD Page 126...

  • Page 127: Uart Registers

    12.7.4 UART n Divisor Latch MSB register (UARTn_DLM) (n=0,1) Address Offset: 0x04 Name Description Attribute Reset 31:8 Reserved The UART Divisor Latch MSB Register, along with the DLL register, DLM[7:0] determines the baud rate of the UART. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 127...

  • Page 128: Uart N Interrupt Enable Register (Uartn_Ie) (N=0, 1)

    1: Auto-baud has finished successfully and interrupt is enabled. FIFOEN Equivalent to FIFOEN bit in UARTn_FIFOCTRL register. Reserved INTID[2:0] Interrupt identification which identifies an interrupt corresponding to the UARTn RX FIFO. 0x3: 1 - Receive Line Status (RLS). Version 1.9 SONiX TECHNOLOGY CO., LTD Page 128...
  • Page 129 3.5 to 4.5 character times. Read UARTn_II register THRE 0010 THRE (if source of interrupt) or Write THR register Read UARTn_II register (if source of interrupt) or TEMT 1110 TEMT Write THR register Version 1.9 SONiX TECHNOLOGY CO., LTD Page 129...

  • Page 130: Uart N Fifo Control Register (Uartn_Fifoctrl) (N=0,1)

    Word Length Select bits WLS[1:0] 00: 5-bit character length. 01: 6-bit character length. 10: 7-bit character length. 11: 8-bit character length. 12.7.9 UART n Line Status register (UARTn_LS) (n=0,1) Address Offset: 0x14 Version 1.9 SONiX TECHNOLOGY CO., LTD Page 130...
  • Page 131 FIFO will not be overwritten and the character in the UARTn_RS register will be lost. 0: Overrun error status is inactive. 1: Overrun error status is active. Receiver Data Ready flag RDR=1 when the UARTn_RB FIFO holds an unread character and is Version 1.9 SONiX TECHNOLOGY CO., LTD Page 131...

  • Page 132: Uart N Scratch Pad Register (Uartn_Sp) (N=0, 1)

     Note: If the fractional divider is active (DIVADDVAL>0) and UARTn_DLM=0, the value of the UARTn_DLL register must ≥ 3. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 132...

  • Page 133: Uart N Control Register (Uartn_Ctrl) (N=0, 1)

    The behavior of the UART is unpredictable when data is presented for reception while data is being transmitted. For this reason, the value of the HDEN register should not be modified while sending or receiving data, or data may be lost or corrupted. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 133...
  • Page 134 SN32F100 Series 32-Bit Cortex-M0 Micro-Controller Name Description Attribute Reset 31:1 Reserved Half-duplex mode enable bit HDEN 0: Disable 1: Enable Version 1.9 SONiX TECHNOLOGY CO., LTD Page 134...

  • Page 135: Audio (I2S/Codec)

    ◇ THD+N: -75dB (+0dBr).  Differential microphone interface. ◇ Programmable gain amplifier (PGA) -12dB~+33dB. ◇ MIC boost gain 0,+12,+20,+30dB. ◇ Auto Gain Control (AGC).  Common mode output interface. ◇ Mute on/off. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 135...

  • Page 136: Pin Description

    13.3.3 Audio Clock Pin Description Pin Name Type Description GPIO Configuration External high-speed X’tal output pin for audio. AUXTALOUT Depends on GPIOn_CFG External high-speed X’tal input pin for audio. AUXTALIN Depends on GPIOn_CFG Version 1.9 SONiX TECHNOLOGY CO., LTD Page 136...

  • Page 137: Block Diagram

    HCLK I2S_PCLK I2S DIV BCLK_O MCLK_O MCLKO_EN 13.4.2 I2S BLOCK DIAGRAM I2SMCLK I2S_CTRL I2SWS I2S CLOCK CONTROL 8 x 32-bit FIFO I2SBCLK I2S_FIFO SERIAL ENCODER I2SDIN I2SDOUT I2S_STATUS I2S Interrupt I2S_RIS I2S_IE Version 1.9 SONiX TECHNOLOGY CO., LTD Page 137...

  • Page 138: 16-Bit Sigma-Delta Adc Block Diagram

    SN32F100 Series 32-Bit Cortex-M0 Micro-Controller 13.4.3 16-Bit Sigma-Delta ADC BLOCK DIAGRAM Version 1.9 SONiX TECHNOLOGY CO., LTD Page 138...

  • Page 139: 16-Bit Sigma-Delta Dac Block Diagram

    SN32F100 Series 32-Bit Cortex-M0 Micro-Controller 13.4.4 16-Bit Sigma-Delta DAC BLOCK DIAGRAM Version 1.9 SONiX TECHNOLOGY CO., LTD Page 139...

  • Page 140: Functional Description

    Channel Length > Data Length: BCLK Channel length Channel length Left Right Data length BCLK Channel length Channel length Left Left Right Justified Data length BCLK Channel length Channel length Right Left Right Justified Data length Version 1.9 SONiX TECHNOLOGY CO., LTD Page 140...
  • Page 141 SN32F100 Series 32-Bit Cortex-M0 Micro-Controller Channel Length = Data Length BCLK BCLK Left Justified BCLK Right Justified Version 1.9 SONiX TECHNOLOGY CO., LTD Page 141...

  • Page 142: I2S Fifo Operaion

    32 bit 13.5.2.2 STEREO 8bit RIGHT +1 LEFT +1 RIGHT LEFT RIGHT +3 LEFT +3 RIGHT +2 LEFT +2 16bit RIGHT LEFT RIGHT +1 LEFT+1 24 bit LEFT RIGHT 32 bit LEFT RIGHT Version 1.9 SONiX TECHNOLOGY CO., LTD Page 142...

  • Page 143: I2S Registers

    1: Reset TX FIFO (TXFIFOLV bit becomes 0, TXFIFOEMPTY bit becomes 1, Data in TX FIFO will be cleared). This bit returns “0” automatically Receiver enable bit RXEN 0: Disable 1: Enable Transmit enable bit TXEN Version 1.9 SONiX TECHNOLOGY CO., LTD Page 143...

  • Page 144: I2S Clock Register (I2S_Clk)

    1: MCLK = MCLK source / 2 2: MCLK = MCLK source / 4 … … n: MCLK = MCLK source / (2*n), n>0 13.6.3 I2S Status register (I2S_STATUS) Address Offset: 0x08 Name Description Attribute Reset 31:21 Reserved Version 1.9 SONiX TECHNOLOGY CO., LTD Page 144...

  • Page 145: I2S Interrupt Enable Register (I2S_Ie)

    RX FIFO underflow interrupt enable bit RXFIFOUDFIEN 0: Disable 1: Enable TX FIFO overflow interrupt enable bit TXFIFOOVFIEN 0: Disable 1: Enable Reserved 13.6.5 I2S Raw Interrupt Status register (I2S_RIS) Address Offset: 0x10 Version 1.9 SONiX TECHNOLOGY CO., LTD Page 145...

  • Page 146: I2S Interrupt Clear Register (I2S_Ic)

    Base Address: 0x4006 4000  Note: Codec ADC Registers are available only when codec mode is selected by I2SMOD=1. 13.7.1 ADC Setting 1 register (ADC_SET1) Address Offset: 0x540 Name Description Attribute Reset Version 1.9 SONiX TECHNOLOGY CO., LTD Page 146...

  • Page 147: Adc Setting 2 Register (Adc_Set2)

    Fs : Audio sampling rate 0000: 1/Fs x 2^(0) 0001: 1/Fs x 2^(1) ……. 1110: 1/Fs x 2^(14) 1111: 1/Fs x 2^(15) 13.7.7 ADC Setting 7 register (ADC_SET7) Address Offset: 0x5A0 Name Description Attribute Reset Version 1.9 SONiX TECHNOLOGY CO., LTD Page 147...

  • Page 148: Adc Setting 8 Register (Adc_Set8)

    13.7.12 ADC Setting 12 register (ADC_SET12) Address Offset: 0x5F0 Name Description Attribute Reset 31:4 Reserved AGC Control. SAT_TH 0x03 Threshold for ADC saturation condition. The saturation condition is for sigma-delta ADC, if there are more than Version 1.9 SONiX TECHNOLOGY CO., LTD Page 148...

  • Page 149: Adc Setting 13 Register (Adc_Set13)

    10: 20-bits 11: 24-bits 13.7.16 ADC Setting 16 register (ADC_SET16) Address Offset: 0x630 Name Description Attribute Reset 31:7 Reserved BOOST Boost setting value when AGC is off 0x00 00: +0dB 01: +12dB Version 1.9 SONiX TECHNOLOGY CO., LTD Page 149...

  • Page 150: Adc Setting 18 Register (Adc_Set18)

    Boost setting value at mute mode when AGC is enabled. 00: +0dB 01: +12dB 10: +20dB 11: +30dB AGC Control. PGA_MUTE_VAL 0x10 PGA setting value at mute mode when AGC is enabled. 00000: Mute Version 1.9 SONiX TECHNOLOGY CO., LTD Page 150...

  • Page 151: Adc Setting 20 Register (Adc_Set20)

    Microphone Bias Output select 0: 0.8*VA 1: 0.9*VA Reserved SEL_MIC P1.7/MIC_P and P1.8/MIC_N function selection 0: General purpose IO 1: Microphone Differential input when ADC is enabled Reserved Microphone input path to mixer enable SEL_MIX_MIC Version 1.9 SONiX TECHNOLOGY CO., LTD Page 151...

  • Page 152: Adc Setting 24 Register (Adc_Set24)

    0 : Mute off DAC_EN_IN DAC Enable 1: Enable 0: Disable SOFT_RSTN Software reset digital circuit . low reset . one MCLK pulse trigger 13.8.3 DAC Setting 3 register (DAC_SET3) Address Offset: 0x020 Version 1.9 SONiX TECHNOLOGY CO., LTD Page 152...

  • Page 153: Dac Setting 4 Register (Dac_Set4)

    Step7: MICB_EN = 1 13.9.2 Sigma-delta ADC Power-down Sequence Step1: ADC_EN = 0 Step2: PGA_EN = 0 Step3: MICBOOST_EN = 0 Step4: MICB_EN = 0 Step5: VREF_EN = 0 Step6: IREF_EN = 0 Version 1.9 SONiX TECHNOLOGY CO., LTD Page 153...

  • Page 154: Sigma-Delta Adc Enable Sequence

    Step6: PD_CLK = 1 13.10.3 Sigma-delta DAC Enable Sequence Step1: DAC Digital Enable (DAC_EN_IN = 1) Step2: MCLK Output Enable (MCLKOEN = 1 and I2S Enable) Step3: DAC Analog Enable (Sigma-delta DAC Power-Up Sequence) Version 1.9 SONiX TECHNOLOGY CO., LTD Page 154...

  • Page 155: 24-Channel Comparator

    De-bounce Comparator Interrupt CM11 P2.11 CMPOUT flag CM12 P2.12 CM13 P2.13 CM14 P2.14 CM15 P2.15 CM16 P3.0 CM17 P3.1 CM18 P3.2 CM19 P3.3 CM20 P3.4 CM21 P3.5 CM22 P3.6 CM23 P3.7 CMCH[4:0] Version 1.9 SONiX TECHNOLOGY CO., LTD Page 155...

  • Page 156: Comparator Operation

    Comparator Positive Signal (Vp) Comparator Negative Signal (Vn) Comparator Output Signal (CMPOUT) Comparator Output Signal After De-bounce Trigger to De-bounce De-bounce End De-bounce End Trigger to De-bounce De-bounce Time De-bounce Time Version 1.9 SONiX TECHNOLOGY CO., LTD Page 156...

  • Page 157: Comparator Application Notice

    Channel 23 of Comparator CM23 Negative Input 0.1uF 14.4 COMPARATOR CONTROL REGISTERS Base Address: 0x4006 6000 14.4.1 Comparator Control register (CMPM) Address Offset: 0x00 Name Description Attribute Reset Comparator control bit. CMPEN Version 1.9 SONiX TECHNOLOGY CO., LTD Page 157...

  • Page 158: Comparator Interrupt Enable Register (Cmp_Ie)

    This register controls whether the interrupt condition in the Comparator controller is enabled. Name Description Attribute Reset 31:1 Reserved Comparator edge trigger interrupt enable. (Comparator interrupt trigger CMPGIE direction refer to CMPG) 0: Disable 1: Enable Version 1.9 SONiX TECHNOLOGY CO., LTD Page 158...

  • Page 159: Comparator Interrupt Status Register (Cmp_Ris)

    0: Comparator edge trigger doesn’t occur. 1: Comparator edge trigger occurs. 14.4.4 Comparator Interrupt Clear register (CMP_IC) Address Offset: 0x18 Name Description Attribute Reset 31:1 Reserved 0: No effect CMPGIC 1: Clear CMPGIF bit. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 159...

  • Page 160: Flash

    The SN32F100 series MCU integrated device feature in-system programmable (ISP) FLASH memory for convenient, upgradeable code storage. The FLASH memory may be programmed via the SONiX 32-bit MCU programming interface or by application code for maximum flexibility. The SN32F100 series MCU provides security options at the disposal of the designer to prevent unauthorized access to information stored in FLASH memory.

  • Page 161: Organization

    15.7 EMBEDDED BOOT LOADER The embedded boot loader is used to reprogram the Flash memory using the UART0 serial interface. This program is located in the Boot ROM and is programmed by SONiX during production. Version 1.9 SONiX TECHNOLOGY CO., LTD...

  • Page 162: Flash Memory Controller (Fmc)

    1. Mass erase the User ROM first. User shall NOT execute this operation in debug mode, since the SWD communication may fail during the mass erase procedure. 2. Update security level. includes: - New option byte programming includes: - Option byte erase - Mass Erase Version 1.9 SONiX TECHNOLOGY CO., LTD Page 162...

  • Page 163: Program Flash Memory

    The read protection is activated by setting the Code Security bytes in Code option. When the Flash memory read protection is changed from protected to unprotected, a Mass Erase of the User ROM is performed by HW before reprogramming the read protection option. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 163...

  • Page 164: Fmc Registers

    15.10.3 Flash Data register (FLASH_DATA) Address offset: 0x0C For Page Program operations, this should be updated by SW to indicate the data to be programmed. Name Description Attribute Reset 31:0 DATA[31:0] Data to be programmed. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 164...

  • Page 165: Flash Address Register (Flash_Addr)

    Note: Write access to this register is blocked when the BUSY bit in the FLASH_STATUS register is set. Name Description Attribute Reset Flash Address 31:0 FAR[31:0] Choose the Flash address to erase when Page Erase is selected, or to program when Page Program is selected. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 165...

  • Page 166: Serial-Wire Debug (Swd)

    FW any more. SONiX provide Boot loader to check the status of P0.2 (BOOT pin) during boot procedure. If P0.2 is Low during Boot procedure, MCU will execute code in Boot loader instead of User code, so SWD function is not disabled.

  • Page 167: Internal Pull-Up/Down Resistors On Swd Pins

    To avoid any uncontrolled IO levels, the device embeds internal pull-up and pull-down resistor on the SWD input pins:  NJTRST: Internal pull-up  SWDIO/JTMS: Internal pull-up  SWCLK/JTCK: Internal pull-down Once a SWD function is disabled by SW, the GPIO controller takes control again. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 167...

  • Page 168: Development Tool

    SN32F100 Series 32-Bit Cortex-M0 Micro-Controller DEVELOPMENT TOOL SONIX provides an Embedded ICE emulator system to offer SN32F100 series MCU firmware development. SN32F100 Embedded ICE Emulator System includes:  SN32F100 Starter-Kit.  SN-LINK-V2  USB cable to provide communications between the SN-LINK-V2 and PC.

  • Page 169: Sn-Link-V2

    32-Bit Cortex-M0 Micro-Controller 17.1 SN-LINK-V2 SN-LINK-V2 is a high speed emulator for SONiX 32-bit MCU. It debugs and programs based on SWD protocol. In addition to debugger functions, the SN-LINK-V2 also may be used as a programmer to load firmware from PC to MCU for engineering production, even mass production.

  • Page 170: Sn32F100 Starter-Kit

    It is a simple platform to develop application as target board not ready. The starter-kit can be replaced by target board because of SN32F100 series MCU integrates SWD debugger circuitry. 17.2.1 SN32F100 Start Kit V1.0 Version 1.9 SONiX TECHNOLOGY CO., LTD Page 170...
  • Page 171 JP48: Codec DAC power connector.  JP49: Codec Driver power connector.  JP34: Headset connector.  JP29: Microphone connector.  JP42: MIC_N connector.  JP43: MIC_P connector.  R30: MIC_BIAS from external bias adjust. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 171...

  • Page 172: Sn32F100 Start Kit V1.1/V1.2

    U4: SN32F109F real chip.  D9: Power LED.  RESET button: External reset trigger source.  WAKEUP button: Trigger source to wake up from deep power-down mode.  Y1: External high-speed X’tal Version 1.9 SONiX TECHNOLOGY CO., LTD Page 172...
  • Page 173  JP34: Headset connector.  JP29: Microphone connector.  JP42: MIC_N connector.  JP43: MIC_P connector.  JP54: MIC_BIAS from chip supply or external bias.  R30: MIC_BIAS from external bias adjust. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 173...

  • Page 174: Electrical Characteristic

    Supply voltage (Vdd)…………………………………………………………………………………………………………………….……………… - 0.3V ~ 3.6V Input in voltage (Vin)…………………………………………………………………………………………………………………….… Vss – 0.2V ~ Vdd + 0.2V Operating ambient temperature (Topr) SN32F107, SN32F108, SN32F109 …………...……………………………..……...…………. ………………… -40C ~ + 85C Storage ambient temperature (Tstor) ………………………………………………………………….………………………………………… –40C ~ + 125C 18.2 ELECTRICAL CHARACTERISTIC Standard Operating Conditions (Typical temperature Ta = 25℃)
  • Page 175 [5] IHRC is disabled, external high X’tal is enabled, and PLL is enabled. [6] ILRC is enabled, IHRC and external X’tal are disabled, and PLL is disabled. [7] All oscillators and analog blocks are turned off. [8] DPDWAKEUP pin is pulled HIGH internally. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 175...

  • Page 176: Characteristic Graphs

    The Graphs in this section are for design guidance, not tested or guaranteed. In some graphs, the data presented are outside specified operating range. This is for information only and devices are guaranteed to operate properly only within the specified range. Version 1.9 SONiX TECHNOLOGY CO., LTD Page 176...
  • Page 177 SN32F100 Series 32-Bit Cortex-M0 Micro-Controller Supply Current V.S. Operating Temperature (Operating Conditions : All pins configured as GPIO outputs driven Low and pull-up resistors disabled and VDD = 3.3V) Version 1.9 SONiX TECHNOLOGY CO., LTD Page 177...

  • Page 178: Flash Rom Programming Pin

    Flash IC / JP3 Pin Assignment Connector Number Name Number Number Number Number Number PGDCLK P0.4 P0.4 P0.4 (CLK) OTPCLK P0.6 P0.6 P0.6 (PGM) PGDIN P0.5 P0.5 P0.5 (OE) VR_DOUT P0.7 P0.7 P0.7 (ALSB/PDB) Version 1.9 SONiX TECHNOLOGY CO., LTD Page 178...

  • Page 179: Package Information

    32-Bit Cortex-M0 Micro-Controller PACKAGE INFORMATION 20.1 LQFP 48 PIN SYMBOLS (mm) 0.05 0.15 1.35 1.45 0.09 0.16 9.00 BSC 7.00 BSC 9.00 BSC 7.00 BSC 0.5 BSC 0.17 0.27 0.45 0.75 1 REF Version 1.9 SONiX TECHNOLOGY CO., LTD Page 179...

  • Page 180: Lqfp 64 Pin

    SN32F100 Series 32-Bit Cortex-M0 Micro-Controller 20.2 LQFP 64 PIN Version 1.9 SONiX TECHNOLOGY CO., LTD Page 180...

  • Page 181: Lqfp 80 Pin

    SN32F100 Series 32-Bit Cortex-M0 Micro-Controller 20.3 LQFP 80 PIN Version 1.9 SONiX TECHNOLOGY CO., LTD Page 181...

  • Page 182: Marking Definition

    SN32F100 Series 32-Bit Cortex-M0 Micro-Controller MARKING DEFINITION 21.1 INTRODUCTION There are many different types in SONiX 32-bit MCU production line. This note lists the marking definitions of all 32-bit MCU for order or obtaining information. 21.2 MARKING INDETIFICATION SYSTEM SN32 X Part No.

  • Page 183: Marking Example

    ..9=09 A=10 B=11 ..1=January Month 2=February ..9=September A=October B=November C=December 03= 2003 Year 04= 2004 05= 2005 06= 2006 ..Version 1.9 SONiX TECHNOLOGY CO., LTD Page 183...
  • Page 184 SONIX product could create a situation where personal injury or death may occur.

This manual is also suitable for:

Sn32f108Sn32f109

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