1. Manuals
  2. Brands
  3. SONIX Manuals
  4. Microcontrollers
  5. SN32F769
  6. User manual

SONIX SN32F769 User Manual

Sn32f760 series; sn32f750 series 32-bit cortex-m0 micro-controller
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
SN32F760/750 Series
USER'S MANUAL
SN32F769/759
SN32F768/758
SN32F767/757
SN32F766/756
SN32F765/755
S
O
N
i
X
S
O
N
i
X
SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.
SONiX TECHNOLOGY CO., LTD
3
2
-
B
i
t
C
o
3
2
-
B
i
t
C
o
r
t
e
x
-
M
0
M
r
t
e
x
-
M
0
M
Page 1
SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
i
c
r
o
-
C
o
n
i
c
r
o
-
C
o
n
t
r
o
l
l
e
r
t
r
o
l
l
e
r
Version 2.0

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the SN32F769 and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for SONIX SN32F769

Summary of Contents for SONIX SN32F769

  • Page 1 SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur.

  • Page 2: Amendent History

    1. Update LCD drive waveform. 2. Add Note for setting the pins which are not pin-out. 2018/10/05 1. Add Boot pin description. 2. Fix maximum F to 16MHz in Electrical Characteristics. ADCLK Version 2.0 SONiX TECHNOLOGY CO., LTD Page 2...

  • Page 3: Table Of Contents

    CODE OPTION TABLE ........................38 CORE REGISTER OVERVIEW ..................... 39 SYSTEM CONTROL..........................40 RESET .............................. 40 3.1.1 POWER-ON RESET (POR) ...................... 40 3.1.2 WATCHDOG RESET (WDT RESET) ..................41 3.1.3 BROWN-OUT RESET....................... 41 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 3...
  • Page 4 AHB Clock Enable register (SYS1_AHBCLKEN) ..............57 3.4.2 APB Clock Prescale register 0 (SYS1_APBCP0) ..............58 3.4.3 APB Clock Prescale register 1 (SYS1_APBCP1) ..............59 3.4.4 APB Clock Prescale register 2 (SYS1_APBCP2) ..............61 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 4...
  • Page 5 GPIO Port n Interrupt Event register (GPIOn_IEV) (n=0,1,2,3) ..........76 5.3.7 GPIO Port n Interrupt Enable register (GPIOn_IE) (n=0,1,2,3) ..........76 5.3.8 GPIO Port n Raw Interrupt Status register (GPIOn_RIS) (n=0,1,2,3) ........77 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 5...
  • Page 6 ADC Interrupt Enable register (ADC_IE)................96 7.6.5 ADC Raw Interrupt Status register (ADC_RIS) ............... 96 16-BIT TIMER WITH CAPTURE FUNCTION ................97 OVERVIEW ............................. 97 FEATURES ............................97 PIN DESCRIPTION ......................... 97 BLOCK DIAGRAM ......................... 98 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 6...
  • Page 7 CT32Bn Timer Counter register (CT32Bn_TC) (n=0,1,2) ............ 118 9.7.3 CT32Bn Prescale register (CT32Bn_PRE) (n=0,1,2) ............119 9.7.4 CT32Bn Prescale Counter register (CT32Bn_PC) (n=0,1,2) ..........119 9.7.5 CT32Bn Count Control register (CT32Bn_CNTCTRL) (n=0,1,2) ......... 119 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 7...
  • Page 8 RTC Second Count register (RTC_SECCNT) ................ 133 11.5.8 RTC Alarm Counter Reload Value register (RTC_ALMCNTV) ..........133 11.5.9 RTC Alarm Count register (RTC_ALMCNT) ................. 134 SPI/SSP .............................. 135 12.1 OVERVIEW ........................... 135 12.2 FEATURES ............................ 135 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 8...
  • Page 9 I2C n Status register (I2Cn_STAT) (n=0,1) ................149 13.8.3 I2C n TX Data register (I2Cn_TXDATA) (n=0,1) ..............150 13.8.4 I2C n RX Data register (I2Cn_RXDATA) (n=0,1) ..............150 13.8.5 I2C n Slave Address 0 register (I2Cn_SLVADDR0) (n=0,1) ..........150 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 9...
  • Page 10 USART n Line Status register (USARTn_LS) (n=0,1) ............167 14.11.8 USART n FIFO Control register (USARTn_FIFOCTRL) (n=0,1)........168 14.11.9 USART n Line Control register (USARTn_LC) (n=0,1) ............ 168 14.11.10 USART n Modem Control register (USARTn_MC) (n=0,1) ..........169 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 10...
  • Page 11 I2S TXFIFO register (I2S_TXFIFO) ..................183 4X32 LCD DRIVER ......................... 184 16.1 OVERVIEW ........................... 184 16.2 FEATURES ............................ 184 16.3 PIN DESCRIPTION ........................184 16.4 BLOCK DIAGRAM ........................185 16.4.1 LCD CLOCK CONTROL ....................... 185 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 11...
  • Page 12 MASS ERASE ........................ 203 17.9 READ PROTECTION ........................203 17.10 HW CHECKSUM........................203 17.11 FMC REGISTERS ........................204 17.11.1 Flash Low Power Control register (FLASH_LPCTRL) ............. 204 17.11.2 Flash Status register (FLASH_STATUS) ................204 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 12...
  • Page 13 22.5 QFN 33 PIN 5 5 ..........................221 MARKING DEFINITION ....................... 222 23.1 INTRODUCTION .......................... 222 23.2 MARKING INDETIFICATION SYSTEM ..................222 23.3 MARKING EXAMPLE ......................... 223 23.4 DATECODE SYSTEM ........................224 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 13...

  • Page 14: Product Overview

    SYSCLK  Operating modes  In-System Programming (ISP) supported Normal, Sleep, Deep-sleep, Power-down, and Deep  Package (Chip form support) power-down LQFP 80/64/48 pin  Serial Wire Debug (SWD) QFN 46/33 pin Version 2.0 SONiX TECHNOLOGY CO., LTD Page 14...
  • Page 15 4x28 LQFP64 32-bitx3 UARTx1 16-bitx3 USARTx1 SN32F757F 32KB 50 MHz 4x18 LQFP48 32-bitx3 UARTx1 16-bitx3 USARTx1 SN32F756J 32KB 50 MHz 4x17 QFN46 32-bitx3 UARTx1 16-bitx3 SN32F755J 32KB 50 MHz UARTx2 QFN33 32-bitx3 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 15...

  • Page 16: System Block Diagram

    SCL0 I2C0 SDA0 CT16B0_PWM[2:0] 16-bit TIMER 0 with PWM CT16B0_CAP0 SCL1 I2C1 SDA1 CT16B1_PWM[2:0] 16-bit TIMER 1 with PWM CT16B1_CAP0 I2SBCLK I2SWS CT16B2_PWM[2:0] I2SDIN 16-bit TIMER 2 with PWM I2SDOUT CT16B2_CAP0 I2SMCLK Version 2.0 SONiX TECHNOLOGY CO., LTD Page 16...

  • Page 17: Clock Generation Block Diagram

    AHB clock for RTC RTCCLKEN RTC_PCLK clock source register block AHB clock for GPIO GPIO block GPIOCLKEN AHB clock for PFPA AHB clock for SRAM PFPA blcok SRAM block AHB clock for FLASH FLASH block Version 2.0 SONiX TECHNOLOGY CO., LTD Page 17...

  • Page 18: Pin Assignment

    SN32F760 Series 32-Bit Cortex-M0 Micro-Controller PIN ASSIGNMENT SN32F769/759F (LQFP 80 pins) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 ● AIN0/P2.0 P3.6/SEG8 AIN1/P2.1 P3.5/SEG7 BOOT/AIN2/P2.2 P3.4/SEG6 AIN3/P2.3 P3.3/SEG5...
  • Page 19 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32  Note: The pins which are not pin-out shall be set correctly to decrease power consumption in low- power modes. Strongly recommended to set these pins as input pull-up. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 19...
  • Page 20 13 14 15 16 17 18 19 20 21 22 23 24  Note: The pins which are not pin-out shall be set correctly to decrease power consumption in low- power modes. Strongly recommended to set these pins as input pull-up. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 20...
  • Page 21 10 11 12 13 14 15 16 17 18 19 20 21 22 23  Note: The pins which are not pin-out shall be set correctly to decrease power consumption in low- power modes. Strongly recommended to set these pins as input pull-up. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 21...
  • Page 22 9 10 11 12 13 14 15 16  Note: The pins which are not pin-out shall be set correctly to decrease power consumption in low- power modes. Strongly recommended to set these pins as input pull-up. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 22...

  • Page 23: Pin Descriptions

    Schmitt trigger structure and built-in pull-up/pull-down resisters as input mode. AIN3~AIN13 — ADC channel input 0~13 pins. P2.14 — Port 2.14 bi-direction pin. P2.14 Schmitt trigger structure and built-in pull-up/pull-down resisters as input mode. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 23...
  • Page 24 SEG21 / URXD1 / SEL0 / MOSI1 / I2SMCLK P0.12 CT16B1_PWM1 / CT16B1_CAP0 SEG20 / UTXD1 / SCK0 / SEL1 / I2SBCLK P0.13 CT16B2_CAP0 / CT32B2_PWM0 P0.14 SEG19 / MOSI0 / SCK1 / I2SWS Version 2.0 SONiX TECHNOLOGY CO., LTD Page 24...
  • Page 25 CT16B2_PWM1 / CT32B1_PWM0 AIN7 / I2SWS P2.7 CT16B1_PWM2 / CT32B2_PWM1 AIN8 / I2SDOUT P2.8 CT16B1_PWM1 / CT32B1_PWM1 / CT32B2_PWM3 AIN9 / I2SWS P2.9 CT16B1_CAP0 / CT16B2_PWM0 / CT32B2_PWM3 P2.10 AIN10 / I2SBCLK Version 2.0 SONiX TECHNOLOGY CO., LTD Page 25...
  • Page 26 VDD, user should manually force to set the I/O port P1.6 and P1.7 as input pull-down state in case of internal power collision. 4. VDD3/VLCD3 is the I/O and LCD driver power input pin for P0.0~P0.7. If VDD3 voltage is lower Version 2.0 SONiX TECHNOLOGY CO., LTD Page 26...
  • Page 27 VDD, user should manually force to set the I/O port P1.6 and P1.7 as input pull-down state in case of internal power collision. 5. VDD1/VLCD1, VDD2/VLCD2, VDD3/VLCD3, and VDD12/VLCD12 power input shall not be floating. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 27...

  • Page 28: Pin Circuit Diagrams

    GPIOn_CFG GPIOPn_MODE Output Bus Output Latch Specific Output Bus *. Specific Output Function Control Bit Specific Input Function Control Bit *. Some specific functions switch I/O direction directly, not through GPIOn_MODE register. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 28...
  • Page 29 I/O Input Bus GPIOn_CFG GPIOPn_MODE Output I/O Output Bus Latch Analog IP Output Terminal *. Specific Output Function Control Bit *. Some specific functions switch I/O direction directly, not through GPIOn_MODE register. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 29...

  • Page 30: Central Processor Unit (Cpu)

    Reserved 0x4001 0000 Reserved 0x4000 C000 CT32B2 0x0001 0000 0x4000 A000 CT32B1 0x4000 8000 64 KB on-chip FLASH CT32B0 0x4000 6000 0x0000 0000 CT16B2 0x4000 4000 CT16B1 0x4000 2000 CT16B0 0x4000 0000 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 30...

  • Page 31: System Tick Timer

    When the counter transitions to zero, the COUNTFLAG status bit is set to 1. The COUNTFLAG bit clears on reads.  Note: When the processor is halted for debugging the counter does not decrease. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 31...

  • Page 32: Systick Usage Hints And Tips

    RELOAD = (system tick clock frequency × 10 ms) −1 = (50 MHz × 10 ms) −1 = 0x0007A11F. Name Description Attribute Reset 31:24 Reserved Value to load into the SYSTICK_VAL when the counter is enabled and 23:0 RELOAD 0x5F7F9B when it reaches 0. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 32...

  • Page 33: System Tick Timer Current Value Register (Systick_Val)

    1: TENMS value is inexact, or not given. 29:24 Reserved Reload value for 10ms timing, subject to system clock skew errors. If the 23:0 TENMS 0xA71FF value reads as zero, the calibration value is not known. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 33...

  • Page 34: Nested Vectored Interrupt Controller (Nvic)

    Settable IRQ8/ 0x0000 0060 Settable IRQ9/ 0x0000 0064 Settable IRQ10/I2C0IRQ I2C0 0x0000 0068 Settable IRQ11/I2C1IRQ I2C1 0x0000 006C Settable IRQ12/ 0x0000 0070 Settable IRQ13/USART0IRQ USART0 0x0000 0074 Settable IRQ14/USART1IRQ USART1 0x0000 0078 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 34...

  • Page 35: Nvic Registers

    1: Enable interrupt. Read 0: Interrupt disabled 1: Interrupt enabled. 2.3.2.2 IRQ0~31 Interrupt Clear-Enable Register (NVIC_ICER) Address: 0xE000 E180 (Refer to Cortex-M0 Spec.) The ICER disables interrupts, and shows the interrupts that are enabled. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 35...

  • Page 36: Irq0~31 Interrupt Set-Pending Register (Nvic_Ispr)

    Each priority field holds a priority value, 0-192. The lower the value, the 23:16 PRI_(4*n+2) greater the priority of the corresponding interrupt. The processor implements only bits[23:22] of each field, bits [21:16] read as zero and ignore writes. This Version 2.0 SONiX TECHNOLOGY CO., LTD Page 36...

  • Page 37: Application Interrupt And Reset Control (Airc)

    1: Requests a system level reset. Reserved for debug use. This bit read as 0. When writing to the register VECTCLRACTIVE you must write 0 to this bit, otherwise behavior is Unpredictable. Reserved Version 2.0 SONiX TECHNOLOGY CO., LTD Page 37...

  • Page 38: Code Option Table

    32-Bit Cortex-M0 Micro-Controller 2.5 CODE OPTION TABLE Address: 0x1FFF 2000 Name Description Attribute Reset 31:16 Code Security[15:0] Code Security 0xFFFF 0xFFFF: CS0 0x5A5A: CS1 0xA5A5: CS2 0x55AA: CS3 15:0 Reserved All 1 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 38...

  • Page 39: Core Register Overview

    These registers are mutually exclusive bit fields in the 32-bit PSR. PRIMASK The PRIMASK register prevents activation of all exceptions with configurable priority. The CONTROL register controls the stack used when the processor is in Thread mode. CONTROL Version 2.0 SONiX TECHNOLOGY CO., LTD Page 39...

  • Page 40: System Control

    System initialization: All system registers is set as initial conditions and system is ready.  Oscillator warm up: Oscillator operation is successfully and supply to system clock.  Program executing: Power on sequence is finished and program executes from Boot loader. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 40...

  • Page 41: Watchdog Reset (Wdt Reset)

    Let system under dead-band includes some conditions. DC application: The power source of DC application is usually using battery. When low battery condition and MCU drive any loading, Version 2.0 SONiX TECHNOLOGY CO., LTD Page 41...

  • Page 42: The System Operating Voltage Decsription

    External reset circuit. (Zener diode reset circuit, Voltage bias reset circuit, External reset IC) Note: The “Zener diode reset circuit”, “Voltage bias reset circuit” and “External reset IC” can completely  improve the brown out reset, DC low battery and AC slow power down conditions. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 42...

  • Page 43: External Reset

    Delay Time The LVD (low voltage detector) is built-in SONiX 32-bit MCU to be brown out reset protection. When the VDD drops and is below LVD detect voltage, the LVD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt;...

  • Page 44: Simply Rc Reset Circuit

    The reset circuit has a simply protection against unusual power. The diode offers a power positive path to conduct higher power to VDD. It is can make reset pin voltage level to synchronize with VDD voltage. The structure can Version 2.0 SONiX TECHNOLOGY CO., LTD Page 44...

  • Page 45: Zener Diode Reset Circuit

    The operating voltage is not accurate as Zener diode reset circuit. Use R1, R2 bias voltage to be the active level. When VDD voltage level is above or equal to “0.7V x (R1 + R2) / R1”, the C terminal of the PNP transistor outputs high Version 2.0 SONiX TECHNOLOGY CO., LTD Page 45...

  • Page 46: External Reset Ic

    The internal reset is deasserted and the MCU loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 46...

  • Page 47: System Clock

    RC type oscillator circuit. The frequency is affected by the voltage and temperature of the system. In common condition, the frequency of the RC oscillator is about 32 KHz.  Note: The ILRC can ONLY be switched on and off by HW. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 47...

  • Page 48: Pll

    3.2.2 SONiX 32-bit MCU uses the PLL to create the clocks for the core and peripherals. The input frequency range is 10MHz to 25MHz. The input clock is divided down and fed to the Phase-Frequency Detector (PFD). This block compares the phase and frequency of its inputs, and generates a control signal when phase and/ or frequency do not match.

  • Page 49: External Clock Source

    Main Purpose: System high clock source, RTC clock source, and PLL clock source.  Warm-up Time: 2048*F  XIN/XOUT Shared Pin Selection: Oscillator Mode XTALIN pin XTALOUT pin GPIO IHRC GPIO Crystal/Ceramic Crystal/Ceramic EHS X’TAL Version 2.0 SONiX TECHNOLOGY CO., LTD Page 49...

  • Page 50: External Low-Speed (Els) Clock

    External clock source the input clock signal. (Bypass) EHS X’tal can have a frequency of up to 25 MHz. Select this mode by setting EHSEN bit Analog Block Control register (SYS0_ANBCTRL). Version 2.0 SONiX TECHNOLOGY CO., LTD Page 50...

  • Page 51: System Clock (Sysclk) Selection

    One of 6 clock signals can be selected as clock output: 1. HCLK 2. IHRC 3. ILRC 4. PLL clock output 5. ELS X’TAL 6. EHS X’TAL The selection is controlled by the CLKOUTSEL bits in SYS1_AHBCLKEN register. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 51...

  • Page 52: System Control Registers 0

    01: EHS X’TAL 10 MHz ~ 25 MHz Other: Reserved 11:9 Reserved FSEL Front divider value. The division value F is the programmed 2 FSEL 0: F = 1 1: F = 2 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 52...

  • Page 53: Recommend Frequency Setting

    RECOMMEND FREQUENCY SETTING / F * M CLKIN CLKOUT (MHz) (MHz) FSEL MSEL[4:0]=M PSEL[2:0] P= PSEL[2:0]*2 (MHz) CLKIN CLKOUT /F*M CLKIN 3.3.3 Clock Source Status register (SYS0_CSST) Address Offset: 0x08 Name Description Attribute Reset Version 2.0 SONiX TECHNOLOGY CO., LTD Page 53...

  • Page 54: System Clock Configuration Register (Sys0_Clkcfg)

    0001: SYSCLK / 2 0010: SYSCLK / 4 0011: SYSCLK / 8 0100: SYSCLK / 16 0101: SYSCLK / 32 0110: SYSCLK / 64 0111: SYSCLK / 128 1000: SYSCLK / 256 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 54...

  • Page 55: System Reset Status Register (Sys0_Rstst)

    Name Description Attribute Reset 31:16 Reserved LVD enable LVDEN 0: Disable 1: Enable LVD Reset enable LVDRSTEN 0: Disable 1: Enable 13:7 Reserved LVD interrupt level LVDINTLVL[2:0] 000: 1.80V 001: 2.00V Version 2.0 SONiX TECHNOLOGY CO., LTD Page 55...

  • Page 56: External Reset Pin Control Register (Sys0_Exrstctrl)

    Attribute Reset 31:1 Reserved SWD pin disable bit. SWDDIS 0: Enable SWD pin. (P0.9 acts as SWDIO pin, P0.8 acts as SWCLK pin) 1: Disable. (P0.8 and P0.9 act as GPIO pins) Version 2.0 SONiX TECHNOLOGY CO., LTD Page 56...

  • Page 57: System Control Registers 1

    USART0CLKEN 0: Disable 1: Enable 15:14 Reserved Enables clock for SSP1. SSP1CLKEN 0: Disable 1: Enable Enables clock for SSP0. SSP0CLKEN 0: Disable 1: Enable Enables clock for ADC. ADCCLKEN 0: Disable Version 2.0 SONiX TECHNOLOGY CO., LTD Page 57...

  • Page 58: Apb Clock Prescale Register 0 (Sys1_Apbcp0)

    001: HCLK / 2 010: HCLK / 4 011: HCLK / 8 100: HCLK / 16 Other: Reserved Reserved SSP0 clock source prescaler 22:20 SSP0PRE[2:0] 000: HCLK / 1 001: HCLK / 2 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 58...

  • Page 59: Apb Clock Prescale Register 1 (Sys1_Apbcp1)

    Other: Reserved 3.4.3 APB Clock Prescale register 1 (SYS1_APBCP1) Address Offset: 0x08  Note: Must reset the corresponding peripheral with SYS1_PRST register after changing the prescale value. Name Description Attribute Reset Reserved Version 2.0 SONiX TECHNOLOGY CO., LTD Page 59...
  • Page 60 100: HCLK / 16 Other: Reserved Reserved USART0 clock source prescaler USART0PRE[2:0] 000: HCLK / 1 001: HCLK / 2 010: HCLK / 4 011: HCLK / 8 100: HCLK / 16 Other: Reserved Version 2.0 SONiX TECHNOLOGY CO., LTD Page 60...

  • Page 61: Apb Clock Prescale Register 2 (Sys1_Apbcp2)

    0: No effect 1: Reset USART1 USART0 reset USART0RST 0: No effect 1: Reset USART0 LCD reset LCDRST 0: No effect 1: Reset LCD Reserved SSP1 reset SSP1RST 0: No effect 1: Reset SSP1 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 61...
  • Page 62 0: No effect 1: Reset GPIO port 2 GPIO port 1 reset GPIOP1RST 0: No effect 1: Reset GPIO port 1 GPIO port 0 reset GPIOP0RST 0: No effect 1: Reset GPIO port 0 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 62...

  • Page 63: Divider Dividend Register (Sys1_Dividend)

    Note: Quotient is 0xFFFFFFFF when Divisor is 0x0, instead of occurring Hard Fault, since FW shall be able to handle this case. Name Description Attribute Reset 31:0 Quotient[31:0] Unsigned integer Quotient 3.4.9 Divider Remainder register (SYS1_REMAINDER) Address Offset: 0x2C Name Description Attribute Reset 31:0 Remainder[31:0] Unsigned integer Remainder Version 2.0 SONiX TECHNOLOGY CO., LTD Page 63...

  • Page 64: Divider Control Register (Sys1_Divctrl)

    Name Description Attribute Reset 31:1 Reserved Divider start control bit. DIVS 0: Divider stops/finishes operation. 1: Start to execute Dividing. DIVS is cleared by HW automatically when the operation of dividing finishes. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 64...

  • Page 65: System Operation Mode

    Peripheral functions, if selected to be clocked in SYS1_AHBCLKEN register, continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used Version 2.0 SONiX TECHNOLOGY CO., LTD Page 65...

  • Page 66: Deep-Sleep Mode

    The processor state and registers, peripheral registers, and internal SRAM values are not retained. However, the chip can retain data in four BACKUP registers, and the status of all GPIO pins can also be latched. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 66...

  • Page 67: Entering Deep Power-Down Mode

    5. Setup the same GPIO status of all GPIO pins as step 2 of 4.3.3.1. 6. Write 0x5A5A0001 to PMU_LATCHCTRL2 register to release the status of all GPIO pins. 7. Setup the PMU for the next Deep power-down cycle. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 67...

  • Page 68: Wakeup

    IHRC  Example: F =12MHz, the wakeup time is as the following. IHRC The total Wakeup time = 2T*ILRC + 1/F * 32 = 62.5us + 2.67 us = 12MHz) IHRC IHRC Version 2.0 SONiX TECHNOLOGY CO., LTD Page 68...

  • Page 69: State Machine Of Pmu

    Wake-up condition Interrupt Wake-up condition GPIO Wakeup Enter mode condition RTC interrupt LCD interrupt 1. PMU_CTRL = 2 2. WFI instruction Reset condition One of reset trigger sources actives Deep-sleep mode Version 2.0 SONiX TECHNOLOGY CO., LTD Page 69...

  • Page 70: Operation Mode Comparsion Table

    RESET pin LCDENB LCDCLK RTCENB RTC_CLKS ILRC* ELS* 0 (ILRC) 1 (ELS) 0 (ILRC) 1 (ELS) 0 (ILRC) 0 (ILRC) 1 (ELS) 1 (ELS) 0 (ILRC) 1 (ELS) 1 (ELS) 0 (ILRC) Version 2.0 SONiX TECHNOLOGY CO., LTD Page 70...

  • Page 71: Pmu Registers

    001: WFI instruction will make MCU enter Deep-power down mode. 010: WFI instruction will make MCU enter Deep-sleep mode. 100: WFI instruction will make MCU enter Sleep mode. Other: Disable 4.7.3 I/O Latch Control register 1 (PMU_LATCHCTRL1) Address Offset: 0x44 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 71...

  • Page 72: I/O Latch Control Register 2 (Pmu_Latchctrl2)

    1: Disable GPIO latch function 4.7.5 I/O Latch Status register (PMU_LATCHST) Address Offset: 0x4C Name Description Attribute Reset 31:1 Reserved Latch status bit LATCH 0: Not Latch yet 1: GPIO status is Latched. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 72...

  • Page 73: General Purpose I/O Port (Gpio)

    LOW. This causes the pin to retain its last known state if it is configured as an input and is not driven externally. The state retention is not applicable to the Deep power-down mode. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 73...

  • Page 74: Gpio Registers

    01: Pull-down resistor enabled. 10: Inactive (no pull-down/pull-up resistor enabled). 11: Repeater mode. Configuration of Pn.14 29:28 CFG14[1:0] 00: Pull-up resistor enabled. 01: Pull-down resistor enabled. 10: Inactive (no pull-down/pull-up resistor enabled). Version 2.0 SONiX TECHNOLOGY CO., LTD Page 74...
  • Page 75 11: Repeater mode. Configuration of Pn.1 CFG1[1:0] 00: Pull-up resistor enabled. 01: Pull-down resistor enabled. 10: Inactive (no pull-down/pull-up resistor enabled). 11: Repeater mode. Configuration of Pn.0 CFG0[1:0] 00: Pull-up resistor enabled. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 75...

  • Page 76: Gpio Port N Interrupt Sense Register (Gpion_Is) (N=0,1,2,3)

    Name Description Attribute Reset 31:16 Reserved Selects interrupt on pin x to be enabled (x = 0 to 15). 15:0 IE[15:0] 0: Disable Interrupt on Pn.x 1: Enable Interrupt on Pn.x Version 2.0 SONiX TECHNOLOGY CO., LTD Page 76...

  • Page 77: Gpio Port N Raw Interrupt Status Register (Gpion_Ris) (N=0,1,2,3)

    Name Description Attribute Reset 31:16 Reserved Bit clear enable (x = 0 to 15) 15:0 BCLR[15:0] 0: No effect on Pn.x 1: Clear Pn.x. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 77...

  • Page 78: Gpio Port N Open-Drain Control Register (Gpion_Odctrl) (N=0,1,2,3)

    Name Description Attribute Reset 31:16 Reserved Open-drain control bit (x = 0 to 15) 15:0 OC[15:0] 0: Disable. 1: Enable open-drain function of Pn.x. HW also set Pn.x as output mode automatically. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 78...

  • Page 79: Peripheral Function Pin Assignment (Pfpa)

    P3.6 P2.10 P2.11 P3.4 P0.14 P1.10 P2.1 P2.7 P2.9 DOUT P3.1 P0.11 P1.7 P3.8 P2.8 P2.12 P3.0 P0.10 P1.6 P3.9 P2.0 P2.5 CT16B0 CAP0 P0.2 P0.8 P1.0 P3.0 P3.2 P3.10 P2.0 P2.13 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 79...

  • Page 80: Pfpa Registers

    Address offset: 0x00 Name Description Attribute Reset 31:16 Reserved Pin to be assigned as URXD1. 15:12 URXD1[3:0] 0000b 0000: P1.0 0001: P0.7 0010: P0.12 0011: P1.5 0100: P1.13 0101: P1.15 0110: P3.6 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 80...

  • Page 81: Pfpa For I2C Register (Pfpa_I2C)

    0010: P1.0 0011: P1.8 0100: P3.2 0101: P3.4 0110: P3.5 0111: P3.12 Other: Reserved Pin to be assigned as SCL0. SCL0[3:0] 0000b 0000: P1.5 0001: P0.2 0010: P0.15 0011: P1.3 0100: P1.14 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 81...

  • Page 82: Pfpa For Ssp Register (Pfpa_Ssp)

    1001: P2.15 Other: Reserved Pin to be assigned as MISO1. 19:16 MISO1[3:0] 0000b 0000: P3.9 0001: P0.4 0010: P0.10 0011: P1.3 0100: P1.10 0101: P3.0 0110: P3.4 0111: P3.12 1000: P2.1 1001: P2.12 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 82...

  • Page 83: Pfpa For I2S Register (Pfpa_I2S)

    Address offset: 0x0C Name Description Attribute Reset 31:20 Reserved Pin to be assigned as I2SDIN. 19:16 DIN[3:0] 0000b 0000: P3.0 0001: P0.10 0010: P1.6 0011: P3.9 0100: P2.0 0101: P2.5 Other: Reserved Version 2.0 SONiX TECHNOLOGY CO., LTD Page 83...

  • Page 84: Pfpa For Ct16B0 Register (Pfpa_Ct16B0)

    0010: P0.10 0011: P1.13 0100: P3.4 0101: P3.12 0110: P2.2 0111: P2.11 Other: Reserved Pin to be assigned as CT16B0_PWM0. PWM0[3:0] 0000b 0000: P0.0 0001: P1.1 0010: P1.8 0011: P1.12 0100: P3.3 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 84...

  • Page 85: Pfpa For Ct16B1 Register (Pfpa_Ct16B1)

    0110: P2.0 0111: P2.12 Other: Reserved Pin to be assigned as CT16B1_CAP0. CAP0[3:0] 0000b 0000: P0.12 0001: P0.7 0010: P1.7 0011: P1.11 0100: P3.5 0101: P3.13 0110: P2.1 0111: P2.9 Other: Reserved Version 2.0 SONiX TECHNOLOGY CO., LTD Page 85...

  • Page 86: Pfpa For Ct16B2 Register (Pfpa_Ct16B2)

    Description Attribute Reset 31:20 Reserved Pin to be assigned as CT32B0_PWM3. 19:16 PWM3[3:0] 0000b 0000: P1.2 0001: P0.3 0010: P0.7 0011: P0.15 0100: P1.12 0101: P3.4 0110: P2.2 0111: P2.12 Other: Reserved Version 2.0 SONiX TECHNOLOGY CO., LTD Page 86...

  • Page 87: Pfpa For Ct32B1 Register (Pfpa_Ct32B1)

    0101: P3.11 0110: P2.4 0111: P2.13 Other: Reserved Pin to be assigned as CT32B1_PWM2. 15:12 PWM2[3:0] 0000b 0000: P1.6 0001: P0.5 0010: P0.8 0011: P0.11 0100: P3.12 0101: P2.5 0110: P2.12 0111: P2.14 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 87...

  • Page 88: Pfpa For Ct32B2 Register (Pfpa_Ct32B2)

    0011: P1.6 0100: P3.1 0101: P3.13 0110: P3.15 0111: P2.14 Other: Reserved Pin to be assigned as CT32B2_PWM1. 11:8 PWM1[3:0] 0000b 0000: P0.14 0001: P0.2 0010: P0.15 0011: P1.5 0100: P3.0 0101: P3.7 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 88...
  • Page 89 0110: P2.11 0111: P2.15 Other: Reserved Pin to be assigned as CT32B2_CAP0. CAP0[3:0] 0000b 0000: P3.7 0001: P0.9 0010: P0.10 0011: P1.4 0100: P1.13 0101: P3.14 0110: P2.5 0111: P2.12 Other: Reserved Version 2.0 SONiX TECHNOLOGY CO., LTD Page 89...

  • Page 90: 14+1 Channel Analog To Digital Convertor (Adc)

    Calibration AIN10 AIN11 ADENB ADT[4:0] AIN12 AIN13 AIN14 (Internal to TS)  Note: 1. For 8-bit resolution the conversion time is 12 steps. For 12-bit resolution the conversion time is 16 steps Version 2.0 SONiX TECHNOLOGY CO., LTD Page 90...

  • Page 91: Adc Converting Time

    ADC Clock [2:0] Conversion Conversion Conversion Conversion Time (us) Rate (KHz) Time (us) Rate (KHz) ADC_PCLK 83.333 333.333 ADC_PCLK/2 41.667 166.667 ADC_PCLK/4 20.83 83.333 ADC_PCLK/8 10.416 41.667 ADC_PCLK/16 5.208 20.83 ADC_PCLK/32 2.604 10.416 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 91...

  • Page 92: Adc Control Notice

    If the ADC high reference voltage is from external voltage source, the external high reference is connected to AVREFH pin (P2.0). The external high reference source must be through a 47uF ”C” capacitor first, and then 0.1uF capacitor “B”. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 92...

  • Page 93: Temperature Sensor (Ts)

    1. The V(TS) voltage and temperature curve of each chip might different. Calibration in room temperature is necessary when temperature sensor is used. ℃ 2. 3.53mV/ is only the typical temperature parameter, every single chip is different to each other. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 93...

  • Page 94: Adc Registers

    0001: AIN1 0010: AIN2 0011: AIN3 0100: AIN4 0101: AIN5 0110: AIN6 0111: AIN7 1000: AIN8 1001: AIN9 1010: AIN10 1011: AIN11 1100: AIN12 1101: AIN13 1110: AIN14 (Temperature Sensor) Other: Reserved Version 2.0 SONiX TECHNOLOGY CO., LTD Page 94...

  • Page 95: Adc Data Register (Adc_Adb)

    P2.x configuration control bits. (x=0 to 15) 15:0 P2CON[15:0] 0: P2.x can be an analog input (ADC input) or digital I/O pins. 1: P2.x is pure analog input, can’t be a digital I/O pin. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 95...

  • Page 96: Adc Interrupt Enable Register (Adc_Ie)

    0: ReadNo interrupt on AINx WriteWrite “0” to the corresponding bit will clear the bit and reset the Interrupt if the corresponding IE bit is set. 1: Interrupt requirements met on AINx ADC conversion. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 96...

  • Page 97: 16-Bit Timer With Capture Function

    – Toggle on match. – Do nothing on match. PIN DESCRIPTION Pin Name Type Description GPIO Configuration CT16Bn_CAP0 Capture channel input 0 Depends on GPIOn_CFG CT16Bn_PWMx Output channel x of Match/PWM output. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 97...

  • Page 98: Block Diagram

    SN32F760 Series 32-Bit Cortex-M0 Micro-Controller BLOCK DIAGRAM MRxSTOP CRST CRST MRxIF STOP STOP MRxIE MRx Interrupt PCLK MRxRST RESET RESET PWMxEN CT16Bn_PWMx PWMxIOEN EMCx CAP0 CAP0EN CT16Bn_CAP0 CAP0FE CAP0IE CAP0 Interrupt CAP0RE Version 2.0 SONiX TECHNOLOGY CO., LTD Page 98...

  • Page 99: Timer Operation

    6. In the next clock after the timer reaches the match value, the CEN bit in CT16Bn_TMRCTRL register is cleared, and the interrupt indicating that a match occurred is generated. PCLK CT16Bn_PC CT16Bn_TC CEN bit Interrupt Version 2.0 SONiX TECHNOLOGY CO., LTD Page 99...

  • Page 100: Edge-Aligned Down-Counting Mode

    Besides, TC is blocked while the value of CT16Bn_MR3 is zero. The following figure shows a timer in Center-aligned counting mode. The CT16Bn_PRE register is set to 0, and the CT16Bn_MR3 register is set to 5. PCLK CT16Bn_TC Version 2.0 SONiX TECHNOLOGY CO., LTD Page 100...

  • Page 101: Pwm

    0, the CT16Bn_MR3 register is set to 8, the CT16Bn_MR2 register is set to 7, the CT16Bn_MR1 register is set to 4, and the CT16Bn_MR0 register is set to 0. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 101...

  • Page 102: Pwm Mode 2

    If a match value larger than the PWM cycle length is written to the CT16Bn_MR0~3 registers, and the PWM signal is LOW already, then the PWM signal will go HIGH on the next start of the next PWM cycle. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 102...
  • Page 103 PWM cycle length. For this register, set the MRnR bit to one to enable the timer reset when the timer value matches the value of the corresponding match register. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 103...

  • Page 104: Ct16B Nregisters

    In Edge-aligned down-counting mode (CM[2:0]=001b) , the TC[15:0] should be reset to the value of CT16Bn_MR3 after resetting counter (SW set CRST to 1). Name Description Attribute Reset 31:16 Reserved 15:0 TC[15:0] Timer Counter Version 2.0 SONiX TECHNOLOGY CO., LTD Page 104...

  • Page 105: Ct16Bn Prescale Register (Ct16Bn_Pre) (N=0,1,2)

    In counter mode (when CTM[1:0] are not 00), these bits select which CAP0 pin is sampled for clocking. 00: CT16Bn_CAP0 Other: Reserved. Counter/Timer Mode. CTM[1:0] This field selects which rising PCLK edges can increment Timer’s Version 2.0 SONiX TECHNOLOGY CO., LTD Page 105...

  • Page 106: Ct16Bn Match Control Register (Ct16Bn_Mctrl) (N=0,1,2)

    Enable reset TC when MR0 matches TC. MR0RST 0: Disable 1: Enable Enable generating an interrupt based on CM[2:0] when MR0 matches the MR0IE value in the TC. 0: Disable 1: Enable Version 2.0 SONiX TECHNOLOGY CO., LTD Page 106...

  • Page 107: Ct16Bn Match Register 0~3 (Ct16Bn_Mr0~3) (N=0,1,2)

    Name Description Attribute Reset 31:16 Reserved 15:0 CAP0[15:0] Timer counter capture value Version 2.0 SONiX TECHNOLOGY CO., LTD Page 107...

  • Page 108: Ct16Bn External Match Register (Ct16Bn_Em) (N=0,1,2)

    1: CT16Bn_PWM1 pin act as match output, and output signal depends on PWM1EN bit. CT16Bn_PWM0/GPIO selection bit PWM0IOEN 0: CT16Bn_PWM0 pin act as GPIO 1: CT16Bn_PWM0 pin act as match output, and output signal depends on PWM0EN bit. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 108...

  • Page 109: Ct16Bn Timer Raw Interrupt Status Register (Ct16Bn_Ris) (N=0,1,2)

    0: No interrupt on match channel 1 1: Interrupt requirements met on match channel 1. Interrupt flag for match channel 0. MR0IF 0: No interrupt on match channel 0 1: Interrupt requirements met on match channel 0. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 109...

  • Page 110: Ct16Bn Timer Interrupt Clear Register (Ct16Bn_Ic) (N=0,1,2)

    0: No effect MR3IC 1: Clear MR3IF bit 0: No effect MR2IC 1: Clear MR2IF bit 0: No effect MR1IC 1: Clear MR1IF bit 0: No effect MR0IC 1: Clear MR0IF bit Version 2.0 SONiX TECHNOLOGY CO., LTD Page 110...

  • Page 111: 32-Bit Timer With Capture Function

    – Toggle on match. – Do nothing on match. 9.3 PIN DESCRIPTION Pin Name Type Description GPIO Configuration CT32Bn_CAP0 Capture channel input 0 Depends on GPIOn_CFG CT32Bn_PWMx Output channel x of Match/PWM output. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 111...

  • Page 112: Block Diagram

    SN32F760 Series 32-Bit Cortex-M0 Micro-Controller 9.4 BLOCK DIAGRAM MRxSTOP CRST CRST MRxIF STOP STOP MRxIE MRx Interrupt PCLK MRxRST RESET RESET PWMxEN CT32Bn_PWMx PWMxIOEN EMCx CAP0 CAP0EN CT32Bn_CAP0 CAP0FE CAP0IE CAP0 Interrupt CAP0RE Version 2.0 SONiX TECHNOLOGY CO., LTD Page 112...

  • Page 113: Timer Operation

    6. In the next clock after the timer reaches the match value, the CEN bit in CT32Bn_TMRCTRL register is cleared, and the interrupt indicating that a match occurred is generated. PCLK CT32Bn_PC CT32Bn_TC CEN bit Interrupt Version 2.0 SONiX TECHNOLOGY CO., LTD Page 113...

  • Page 114: Edge-Aligned Down-Counting Mode

    Besides, TC is blocked while the value of CT32Bn_MR3 is zero. The following figure shows a timer in Center-aligned counting mode. The CT32Bn_PRE register is set to 0, and the CT32Bn_MR3 register is set to 5. PCLK CT16Bn_TC Version 2.0 SONiX TECHNOLOGY CO., LTD Page 114...

  • Page 115: Pwm

    0, the CT32Bn_MR3 register is set to 8, the CT32Bn_MR2 register is set to 7, the CT32Bn_MR1 register is set to 4, and the CT32Bn_MR0 register is set to 0. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 115...

  • Page 116: Pwm Mode 2

    If a match value larger than the PWM cycle length is written to the CT32Bn_MR0~3 registers, and the PWM signal is LOW already, then the PWM signal will go HIGH on the next start of the next PWM cycle. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 116...
  • Page 117 PWM cycle length. For this register, set the MRnR bit to one to enable the timer reset when the timer value matches the value of the corresponding match register. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 117...

  • Page 118: Ct32B Nregisters

    In Edge-aligned down-counting mode (CM[2:0]=001b) , the TC[31:0] should be reset to the value of CT32Bn_MR3 after resetting counter (SW set CRST to 1). Name Description Attribute Reset 31:0 TC[31:0] Timer Counter Version 2.0 SONiX TECHNOLOGY CO., LTD Page 118...

  • Page 119: Ct32Bn Prescale Register (Ct32Bn_Pre) (N=0,1,2)

    This field selects which rising PCLK edges can clear PC and increment Timer Counter (TC). 00: Timer Mode: every rising PCLK edge 01: Counter Mode: TC is incremented on rising edges on the CAP input Version 2.0 SONiX TECHNOLOGY CO., LTD Page 119...

  • Page 120: Ct32Bn Match Control Register (Ct32Bn_Mctrl) (N=0,1,2)

    The Match register values are continuously compared to the Timer Counter (TC) value. When the two values are equal, actions can be triggered automatically. The action possibilities are to generate an interrupt, reset the Timer Counter, or stop the timer. Actions are controlled by the settings in the CT32Bn_MCTRL register. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 120...

  • Page 121: Ct32Bn Capture Control Register (Ct32Bn_Capctrl) (N=0,1,2)

    If the match outputs are configured as PWM output, the function of the external match registers is determined by the rules. Name Description Attribute Reset 31:12 Reserved Determines the functionality of CT32Bn_PWM3. 11:10 EMC3[1:0] Version 2.0 SONiX TECHNOLOGY CO., LTD Page 121...

  • Page 122: Ct32Bn Pwm Control Register (Ct32Bn_Pwmctrl) (N=0,1,2)

    1: CT32Bn_PWM1 pin act as match output, and output signal depends on PWM1EN bit. CT32Bn_PWM0/GPIO selection bit PWM0IOEN 0: CT32Bn_PWM0 pin act as GPIO 1: CT32Bn_PWM0 pin act as match output, and output signal depends on PWM0EN bit. 19:12 Reserved Version 2.0 SONiX TECHNOLOGY CO., LTD Page 122...

  • Page 123: Ct32Bn Timer Raw Interrupt Status Register (Ct32Bn_Ris) (N=0,1,2)

    0: No interrupt on match channel 1 1: Interrupt requirements met on match channel 1. Interrupt flag for match channel 0. MR0IF 0: No interrupt on match channel 0 1: Interrupt requirements met on match channel 0. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 123...

  • Page 124: Ct32Bn Timer Interrupt Clear Register (Ct32Bn_Ic) (N=0,1,2)

    0: No effect MR3IC 1: Clear MR3IF bit 0: No effect MR2IC 1: Clear MR2IF bit 0: No effect MR1IC 1: Clear MR1IF bit 0: No effect MR0IC 1: Clear MR0IF bit Version 2.0 SONiX TECHNOLOGY CO., LTD Page 124...

  • Page 125: Watchdog Timer (Wdt)

    The clock to the watchdog register block can be disabled in AHB Clock Enable register (SYS1_AHBCLKEN) register for power savings. Watchdog reset or interrupt will occur any time the watchdog is running and has an operating clock source. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 125...

  • Page 126: Block Diagram

    SN32F760 Series 32-Bit Cortex-M0 Micro-Controller 10.2 BLOCK DIAGRAM Feed Watchdog WDT_TC WDT_FEED Feed OK Reload Counter WDT_PCLK /128 8-bit Down Counter Enable Counter underflow WDT_CFG WDINT WDTIE WDTEN WDT Reset WDT Interrupt Version 2.0 SONiX TECHNOLOGY CO., LTD Page 126...

  • Page 127: Wdt Registers

    WDT_PCLK WDT_PCLK 128 x 256. Watchdog overflow time = (0.02us x 1) x 128 x 1 ~ (0.0625ms x 32) x 128 x 256 = 2.56us ~ 65536ms Name Description Attribute Reset Version 2.0 SONiX TECHNOLOGY CO., LTD Page 127...

  • Page 128: Watchdog Feed Register (Wdt_Feed)

    WDKEY, otherwise behavior of writing to the register is ignored. Feed value (Read as 0x0) 15:0 FV[15:0] 0x55AA: The watchdog is fed, and the WDT_TC value is reloaded in the watchdog counter. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 128...

  • Page 129: Real-Time Clock (Rtc)

    The RTC Overflow interrupt flag (OVFIF) is asserted on the last RTC Core clock cycle before the counter reaches 0x0. The RTC Alarm interrupt flag (ALMIF) are asserted on the last RTC Core clock cycle before the counter reaches the RTC Alarm counter reload value stored in the Alarm register. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 129...

  • Page 130: Rtc Operation

    The following figure shows the RTC waveform when it is configured with RTC_SECCNTV=3, RTC_ALMCNTV=0x1000. …… RTC_PCLK …… RTC_SECCNT Cleared by SW …… RTC_SECIF …… RTC_ALMCNT 0x9FF 0x1000 0x1001 …… RTC_ALMIF RTC_PCLK RTC_SECCNT RTC_ALMCNT 0xFFFFFFFF 0xFFFFFFFD 0xFFFFFFFE Cleared by SW RTC_OVFIF Version 2.0 SONiX TECHNOLOGY CO., LTD Page 130...

  • Page 131: Block Diagram

    SN32F760 Series 32-Bit Cortex-M0 Micro-Controller 11.4 BLOCK DIAGRAM EHS_XTAL/128 ELS_XTAL SRC_SEL ILRC CLKSEL RTCEN SECIE SEC_CNT_CLK SECOND Interrupt RTC_SECCNTV RTC_SECCNT SECOND ALMIE ALARM Interrupt RTC_ALMCNTV RTC_ALMCNT OVERFLOW Interrupt OVFIE Version 2.0 SONiX TECHNOLOGY CO., LTD Page 131...

  • Page 132: Rtc Registers

    Overflow interrupt enable OVFIE 0: Disable 1: Enable Alarm interrupt enable ALMIE 0: Disable 1: Enable Second interrupt enable SECIE 0: Disable 1: Enable 11.5.4 RTC Raw Interrupt Status register (RTC_RIS) Address offset: 0x0C Version 2.0 SONiX TECHNOLOGY CO., LTD Page 132...

  • Page 133: Rtc Interrupt Clear Register (Rtc_Ic)

    The RTC core has one 32-bit programmable counter, and this register keeps the current counting value of this counter. Name Description Attribute Reset RTC second counter 31:0 SECCNT[31:0] The current value of the RTC counter. 11.5.8 RTC Alarm Counter Reload Value register (RTC_ALMCNTV) Address offset: 0x1C Reset value: 0xFFFFFFFF Version 2.0 SONiX TECHNOLOGY CO., LTD Page 133...

  • Page 134: Rtc Alarm Count Register (Rtc_Almcnt)

    The zero value is not recommended, and will be replaced with default value (0xFFFFFFFF) by HW. 11.5.9 RTC Alarm Count register (RTC_ALMCNT) Address offset: 0x20 Name Description Attribute Reset RTC alarm counter 31:0 ALMCNT[31:0] The current value of the RTC alarm counter. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 134...

  • Page 135: Spi/Ssp

    SSP Slave Select (Slave) Depends on GPIOn_CFG MISOn Master In Slave Out (Master) Depends on GPIOn_CFG Master In Slave Out (Slave) Master Out Slave In (Master) MOSIn Master Out Slave In (Slave) Depends on GPIOn_CFG Version 2.0 SONiX TECHNOLOGY CO., LTD Page 135...

  • Page 136: Interface Description

    The SPI data transfer timing as following figure: MLSB CPOL CPHA Idle Diagrams Status bit1 High bit1 bit1 Next data High bit1 Next data bit1 High bit1 bit1 Next data High bit1 Next data Version 2.0 SONiX TECHNOLOGY CO., LTD Page 136...

  • Page 137: Ssi

    SCK. The received data is transferred from the serial shifter to the receive FIFO on the first rising edge of SCK after the LSB has been latched. 12.4.3 COMMUNICATION FLOW 12.4.3.1 SINGLE-FRAME CPOL=0 CPHA=1 CPOL=1 CPHA=0 CPOL=1 CPHA=1 CPOL=0 CPHA=0 DATA DATA DATA Version 2.0 SONiX TECHNOLOGY CO., LTD Page 137...

  • Page 138: Multi-Frame

    The Auto-SEL function is disabled (SELDIS = 1) by default, HW does NOT control SELn pin at all, and SELn pin is GPIO. If Auto-SEL function is enabled (SELDIS = 0), SPI HW controls the SELn activity, and SELn is assigned by PFPA_SSP register. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 138...

  • Page 139: Ssp Registers

    Slave data output disable bit (ONLY used in slave mode) SDODIS 0: Enable slave data output. 1: Disable slave data output. (MISO=0) Loop back mode enable LOOPBACK 0: Disable 1: Data input from data output SSP enable bit SSPEN Version 2.0 SONiX TECHNOLOGY CO., LTD Page 139...

  • Page 140: Ssp N Control Register 1 (Sspn_Ctrl1) (N=0,1)

    RX FIFO empty flag RX_EMPTY 0: RX FIFO is NOT empty. 1: RX FIFO is empty. TX FIFO full flag. TX_FULL 0: TX FIFO is NOT full. 1: TX FIFO is full. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 140...

  • Page 141: Ssp N Interrupt Enable Register (Sspn_Ie) (N=0,1)

    RXOVF occurs when the RX FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. 0: RXOVF doesn’t occur. 1: RXOVF occurs. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 141...

  • Page 142: Ssp N Interrupt Clear Register (Sspn_Ic) (N=0,1)

    0s. 12.6.9 SSP n Data Fetch register (SSPn_DF) (n=0,1) Address Offset: 0x20 Name Description Attribute Reset 31:1 Reserved SSP data fetch control bit 0: Disable 1: Enable when SCKn frequency > 6MHz Version 2.0 SONiX TECHNOLOGY CO., LTD Page 142...

  • Page 143: I2C

    Programmable clock allows adjustment of I2C transfer rates.  Data transfer is bidirectional between masters and slaves.  Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 143...

  • Page 144: Pin Description

    I2C Serial clock Output with Open-drain Input depends on GPIOn_CFG SDAn I2C Serial data Output with Open-drain Input depends on GPIOn_CFG 13.4 WAVE CHARACTERISTICS Data Data START STOP Change Change Signal Signal Allowed Allowed Version 2.0 SONiX TECHNOLOGY CO., LTD Page 144...

  • Page 145: I2C Master Modes

    “not acknowledge” to the bus. Arbitration is lost when another device on the bus pulls this signal low. Since this can occur only at the end of a serial byte, the I2C block generates no further clock pulses. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 145...

  • Page 146: I2C Slave Modes

    13.6 I2C SLAVE MODES 13.6.1 SLAVE TRANSMITTER MODE R/W=0 Receiving Address Transmission Data R/W=1 ACK_ ACK_ 13.6.2 SLAVE RECEIVER MODE Receiving Address Receiving Data Receiving Data R/W=0 ACK_ ACK_ ACK_ Terminate by Master Version 2.0 SONiX TECHNOLOGY CO., LTD Page 146...

  • Page 147: Monitor Mode

    Whether any such hardware will be added is still to be determined. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 147...

  • Page 148: I2C Registers

    1: An ACK will be returned during the acknowledge clock pulse on SCLn when  The address in the Slave Address register has been received.  The General Call address has been received while the General Version 2.0 SONiX TECHNOLOGY CO., LTD Page 148...

  • Page 149: I2C N Status Register (I2Cn_Stat) (N=0,1)

    1: MASTER mode a START bit was issued. SLAVE modea START bit was received. Stop done status STOP_DN 0: No STOP bit. 1: MASTER modea STOP condition was issued. SLAVE modea STOP condition was received. NACK done status NACK_STAT Version 2.0 SONiX TECHNOLOGY CO., LTD Page 149...

  • Page 150: I2C N Tx Data Register (I2Cn_Txdata) (N=0,1)

    ADD[9:0] is valid when ADD_MODE = 1 ADD[7:1] is valid when ADD_MODE = 0 13.8.6 I2C n Slave Address 1~3 register (I2Cn_SLVADDR1~3) (n=0,1) Address Offset: 0x14, 0x18, 0x1C Name Description Attribute Reset 31:10 Reserved Version 2.0 SONiX TECHNOLOGY CO., LTD Page 150...

  • Page 151: I2C N Scl High Time Register (I2Cn_Sclht) (N=0,1)

    ACK) onto the I2C data bus. Depending on the state of the SCLOEN bit, the SCL output may be also forced high to prevent the module from having control over the I2C clock line. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 151...
  • Page 152 1: I2C module may act as a slave peripheral just like in normal operation, the I2C holds the clock line low until it has had time to respond to an I2C interrupt. Monitor mode enable bit. MMEN 0: Disable 1: Enable. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 152...

  • Page 153: Universal Synchronous And Asynchronous Receiver And Transmitter (Usart)

    UART is ready to exchange data. The RTS output signal can URTSn be set to an active low by programming bit 1 (RTS) of USARTn_MC register. Loop mode operation holds this signal in its inactive state. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 153...

  • Page 154: Block Diagram

    SN32F760 Series 32-Bit Cortex-M0 Micro-Controller 14.4 BLOCK DIAGRAM MODEM UTXD USARTn_TH UCTS URTS UART Baud Rate Generator INTERRUPT USARTn_RB URXD USARTn_IE USARTn_II USARTn_FC USARTn_LS USARTn_LC Version 2.0 SONiX TECHNOLOGY CO., LTD Page 154...

  • Page 155: Eia-485/Rs-485 Modes

    Set ADCEN bit in USARTn_RS485CTRL register to enable this feature. The ADCEN bit takes precedence over all other mechanisms controlling the direction control pin with the exception of loopback mode. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 155...

  • Page 156: Rs485/Eia-485 Driver Delay Time

    The value of MULVAL and DIVADDVAL should comply with the following conditions: 1. 1 ≤ MULVAL ≤ 15 2. 0 ≤ DIVADDVAL ≤ 14 3. DIVADDVAL< MULVAL 4. Oversampling is 8 or 16 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 156...
  • Page 157 USARTn_PCLK UART BAUDRATE Oversampling x (256 x DLM + DLL) x (1 + DIVADDVAL / MULVAL) 12000000 115200 = 16 x (256 x DLM + DLL) x (1 + DIVADDVAL / MULVAL) Version 2.0 SONiX TECHNOLOGY CO., LTD Page 157...

  • Page 158: Modem Control (Mc)

    The URTS output will be reasserted as soon as the receive FIFO hits the previous trigger level: 4 bytes. … URXD Start Byte N Stop Start Bit 0~7 Stop Stop Start Bit 0~7 URTS Read USARTn RX FIFO … USARTn RX FIFO Level … … Version 2.0 SONiX TECHNOLOGY CO., LTD Page 158...

  • Page 159: Auto-Cts

    The auto-baud function can generate two interrupts.  The ABTOINT interrupt in USARTn_II register will get set if the interrupt is enabled (ABTOIE bit in USARTn_IE register is set and the auto-baud rate measurement counter overflows). Version 2.0 SONiX TECHNOLOGY CO., LTD Page 159...

  • Page 160: Auto-Baud Modes

    Parity Stop Start bit LSB of “A” or “a” URXD START bit in USARTn_ABCTRL Rate Counter 16 x Baud Rate 16 Cycles 16 Cycles  AUTO-BAUD RATE MODE 1 Waveform Version 2.0 SONiX TECHNOLOGY CO., LTD Page 160...

  • Page 161: Smart Card Mode

    If no NACK is sent, the next byte may be transmitted immediately after the last guard bit. If the NACK is sent, the transmitter will retry sending the byte until successfully received or until the SCICTRL retry limit has been met. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 161...

  • Page 162: Synchronous Mode

    These bits should not be changed while the transmitter or the receiver is enabled (TXEN=1 and RXEN=1).  The Synchronous mode supports master mode only, it can NOT receive or send data related to an input clock (SCLK is always an output). Version 2.0 SONiX TECHNOLOGY CO., LTD Page 162...
  • Page 163 SN32F760 Series 32-Bit Cortex-M0 Micro-Controller SCLK CPOL CPHA Idle Diagrams Status bit1 High bit1 bit1 Next data High bit1 Next data Version 2.0 SONiX TECHNOLOGY CO., LTD Page 163...

  • Page 164: Usart Registers

    Reserved The USART Divisor Latch LSB Register, along with the DLM register, DLL[7:0] determines the baud rate of the USART. 14.11.4 USART n Divisor Latch MSB register (USARTn_DLM) (n=0,1) Address Offset: 0x04 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 164...

  • Page 165: Usart N Interrupt Enable Register (Usartn_Ie) (N=0,1)

    The interrupts are frozen during a USARTn_II register access. If an interrupt occurs during a USARTn_II register access, the interrupt is recorded for the next USARTn_II register access. Name Description Attribute Reset Version 2.0 SONiX TECHNOLOGY CO., LTD Page 165...
  • Page 166 (if source of interrupt) or THRE 0010 THRE Write THR register 0000 Lowest CTS, DSR, RI, or DCD. MSR Read Read USARTn_II register (if source of interrupt) or TEMT 1110 TEMT Write THR register Version 2.0 SONiX TECHNOLOGY CO., LTD Page 166...

  • Page 167: Usart N Line Status Register (Usartn_Ls) (N=0,1)

    A USARTn_LS register read clears PE bit. Time of parity error detection is dependent on FIFOEN bit in USARTn_FIFOCTRL register. 0: Parity error status is inactive. 1: Parity error status is active. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 167...

  • Page 168: Usart N Fifo Control Register (Usartn_Fifoctrl) (N=0,1)

    0: Disable access to Divisor Latches. 1: Enable access to Divisor Latches. Break Control bit 0: Disable break transmission. 1: Enable break transmission. Output pin USART TXD is forced to logic 0. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 168...

  • Page 169: Usart N Modem Control Register (Usartn_Mc) (N=0,1)

    Reserved Delta CTS. DCTS Set upon state change of input CTS. Cleared after reading this register. 0: No change detected on modem input CTS. 1: State change detected on modem input CTS. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 169...

  • Page 170: Usart N Scratch Pad Register (Usartn_Sp) (N=0,1)

    OVER8 bit allows software to control the ratio between the input clock and bit clock. This is required for smart card mode, and provides an alternative to fractional division for other modes.  Note: If the fractional divider is active (DIVADDVAL>0) and USARTn_DLM=0, the value of the USARTn_DLL Version 2.0 SONiX TECHNOLOGY CO., LTD Page 170...

  • Page 171: Usart N Control Register (Usartn_Ctrl) (N=0,1)

    011: Smart Card mode. HW will switch GPIO to UTXDn, and enable UTXDn pin with open-drain. 100: Synchronous mode. HW will switch GPIO to UTXDn, URXDn , and USCLK pin. 101:RS-485 mode. HW will switch GPIO to UTXDn, URXDn pin. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 171...

  • Page 172: Usart N Half-Duplex Enable Register (Usartn_Hden) (N=0,1)

    Protocol selection as defined in the ISO7816-3 standard. PROTSEL 0: T = 0 1: T = 1 NACK response disable bit. Only applicable in T=0. NACKDIS 0: A NACK response is enabled. 1: A NACK response is inhibited. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 172...

  • Page 173: Usart N Rs485 Control Register (Usartn_Rs485Ctrl) (N=0,1)

    This delay time is in periods of the baud clock. Any delay time from 0 to 255 bit times may be programmed. Name Description Attribute Reset 31:8 Reserved The direction control (RTS) delay value. This register works in conjunction DLY[7:0] with an 8-bit counter. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 173...

  • Page 174: Usart N Synchronous Mode Control Register (Usartn_Syncctrl) (N=0,1)

    0: Sample on the rising edge of SCLK 1: Sample on the falling edge of SCLK Clock polarity selection bit CPOL 0: SCLK idles at Low level. 1: SCLK idles at High level. Reserved Version 2.0 SONiX TECHNOLOGY CO., LTD Page 174...

  • Page 175: I2S

    I2S Word Select (Slave) Depends on GPIOn_CFG I2SDIN I2S Received Serial data Depends on GPIOn_CFG I2SDOUT I2S Transmitted Serial data I2S Master clock output I2SMCLK I2S Master clock input from GPIO Depends on GPIOn_CFG Version 2.0 SONiX TECHNOLOGY CO., LTD Page 175...

  • Page 176: Block Diagram

    MCLK_O MCLKO_EN 15.4.2 I2S BLOCK DIAGRAM I2SMCLK I2S_CTRL I2SWS I2S CLOCK CONTROL 8 x 32-bit TX FIFO I2SBCLK 8 x 32-bit RX FIFO SERIAL ENCODER I2SDIN I2SDOUT I2S_STATUS I2S Interrupt I2S_RIS I2S_IE Version 2.0 SONiX TECHNOLOGY CO., LTD Page 176...

  • Page 177: Functional Description

    Channel Length > Data Length: BCLK Channel length Channel length Left Right Data length BCLK Channel length Channel length Left Left Right Justified Data length BCLK Channel length Channel length Right Left Right Justified Data length Version 2.0 SONiX TECHNOLOGY CO., LTD Page 177...
  • Page 178 SN32F760 Series 32-Bit Cortex-M0 Micro-Controller Channel Length = Data Length BCLK BCLK Left Justified BCLK Right Justified Version 2.0 SONiX TECHNOLOGY CO., LTD Page 178...

  • Page 179: I2S Fifo Operaion

    32 bit 15.5.2.2 STEREO 8bit RIGHT +1 LEFT +1 RIGHT LEFT RIGHT +3 LEFT +3 RIGHT +2 LEFT +2 16bit RIGHT LEFT RIGHT +1 LEFT+1 24 bit LEFT RIGHT 32 bit LEFT RIGHT Version 2.0 SONiX TECHNOLOGY CO., LTD Page 179...

  • Page 180: I2S Registers

    1, Data in TX FIFO will be cleared). This bit returns “0” automatically Receiver enable bit RXEN 0: Disable 1: Enable Transmit enable bit TXEN 0: Disable 1: Enable I2S operation format. FORMAT[1:0] 00: Standard I2S format Version 2.0 SONiX TECHNOLOGY CO., LTD Page 180...

  • Page 181: I2S Clock Register (I2S_Clk)

    RX FIFO used level 20:17 RXFIFOLV[3:0] 0000: 0/8 RX FIFO is used (Empty) 0001: 1/8 RX FIFO is used 0010: 2/8 RX FIFO is used … … 1000: 8/8 RX FIFO is used (Full) Version 2.0 SONiX TECHNOLOGY CO., LTD Page 181...

  • Page 182: I2S Interrupt Enable Register (I2S_Ie)

    RX FIFO underflow interrupt enable bit RXFIFOUDFIEN 0: Disable 1: Enable TX FIFO overflow interrupt enable bit TXFIFOOVFIEN 0: Disable 1: Enable Reserved 15.6.5 I2S Raw Interrupt Status register (I2S_RIS) Address Offset: 0x10 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 182...

  • Page 183: I2S Interrupt Clear Register (I2S_Ic)

    Address Offset: 0x18 Name Description Attribute Reset 31:0 RXFIFO[31:0] 8 x 32-bit RX FIFO 15.6.8 I2S TXFIFO register (I2S_TXFIFO) Address Offset: 0x1C Name Description Attribute Reset 31:0 TXFIFO[31:0] 8 x 32-bit TX FIFO Version 2.0 SONiX TECHNOLOGY CO., LTD Page 183...

  • Page 184: 4X32 Lcd Driver

    VLCD1 LCD driver power input pin for COM0~3, SEG0~11 VLCD2 LCD driver power input pin for SEG12~23 VLCD3 LCD driver power pin for SEG24~31 2/3 VLCD bias voltage 1/3 VLCD bias voltage Version 2.0 SONiX TECHNOLOGY CO., LTD Page 184...

  • Page 185: Block Diagram

    SEGSEL2 LCD_PCLK R-String VLCD1 VLCD2 LCDREF[1:0] LCD Voltage Multiplexer VLCD3 LCDENB, LCDTYPE LCDBNK COM3 COM2 COM Output Driver VLCD 1C Pump V3/V2 Generator COM1 LCD_CLK COM0 VLCD DUTY[1:0] BIAS VCP[3:0] 4C Pump Version 2.0 SONiX TECHNOLOGY CO., LTD Page 185...

  • Page 186: Lcd Timing

    16.5.2 LCD Driver Waveform LCD Clock 1 Frame 1 Frame VLCD COM0 1/2*VLCD VLCD COM1 1/2*VLCD VLCD COM2 1/2*VLCD VLCD COM3 1/2*VLCD VLCD SEG0 (1010b) 1/2*VLCD VLCD SEG0 (0101b) 1/2*VLCD 1/4 duty, 1/2 bias Version 2.0 SONiX TECHNOLOGY CO., LTD Page 186...
  • Page 187 1 Frame VLCD 2/3*VLCD COM0 1/3*VLCD VLCD 2/3*VLCD COM1 1/3*VLCD VLCD 2/3*VLCD COM2 1/3*VLCD VLCD 2/3*VLCD COM3 1/3*VLCD VLCD 2/3*VLCD SEG0 (1010b) 1/3*VLCD VLCD 2/3*VLCD SEG0 (0101b) 1/3*VLCD 1/4 duty, 1/3 bias Version 2.0 SONiX TECHNOLOGY CO., LTD Page 187...

  • Page 188: R-Type Lcd Application Circuit

    Segment 24~Segment 31 pins are shared with P0.0~P0.7. When these pins are used as LCD pins, the SEG2SEL bit shall be set as “1”, and VLCD3 shall also be connected to VDD with PCB layout. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 188...

  • Page 189: C-Type Lcd Application Circuit

    SEG1SEL bit shall be set as “1”, and VLCD2 shall also be connected to VLCD1 with PCB layout. Segment 24~Segment 31 pins are shared with P0.0~P0.7. When these pins are used as LCD pins, the SEG2SEL bit Version 2.0 SONiX TECHNOLOGY CO., LTD Page 189...

  • Page 190: Type

    1/3Bias (V3= 2/3*VLCD, V2 = 1/3*VLCD) 1/2Bias (V3 = V2 = 1/2*VLCD) LCD Panel LCD Panel SEG0~11 SEG0~11 0.1uF 0.1uF SEG1SEL = 0 VLCD1 VLCD1 SEG2SEL = 0 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF Version 2.0 SONiX TECHNOLOGY CO., LTD Page 190...
  • Page 191 VLCD3 VLCD3 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF LCD Panel LCD Panel SEG0~31 SEG0~31 0.1uF 0.1uF VLCD1 VLCD1 VLCD2 VLCD2 SEG1SEL = 1 VLCD3 VLCD3 SEG2SEL = 1 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF Version 2.0 SONiX TECHNOLOGY CO., LTD Page 191...

  • Page 192: Type

    SEG1SEL = 1 LCD Panel LCD Panel SEG0~11 SEG0~11 VLCD1 VLCD1 VLCD2 SEG2SEL = 1 SEG1SEL = 1 & SEG2SEL = 1 LCD Panel LCD Panel SEG0~11 SEG0~31 VLCD1 VLCD2 VLCD1 VLCD3 VLCD3 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 192...

  • Page 193: Lcd Display Memory Map

    COM3 COM2 SEG27 SEG19 SEG11 SEG3 COM1 COM0 COM3 COM2 SEG26 SEG18 SEG10 SEG2 COM1 COM0 COM3 COM2 SEG25 SEG17 SEG9 SEG1 COM1 COM0 COM3 COM2 SEG24 SEG16 SEG8 SEG0 COM1 COM0 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 193...

  • Page 194: Lcd Registers

    SEG12~23 enable bit SEGSEL1 0: Disable. SEG12~23 pins are GPIO. 1: Enable. HW will assign SEG12~23 pins as LCD pins instead of GPIO. LCD Bias selection BIAS 0: 1/3 Bias 1: 1/2 Bias Version 2.0 SONiX TECHNOLOGY CO., LTD Page 194...

  • Page 195: Lcd Control Register 1(Lcd_Ctrl1)

    The only value “01b” is allowed. 31:30 Reserved Used for internal testing and the only value “00b” is allowed. 29:28 IT1[1:0] Used for internal testing and the only value “0100b” is allowed. 27:24 IT2[3:0] Version 2.0 SONiX TECHNOLOGY CO., LTD Page 195...

  • Page 196: Lcd C-Type Control Register 2 (Lcd_Cctrl2)

    16.9.5 LCD Frame Counter Control register (LCD_FCC) Address offset: 0x10 Reset value: 0x0000 0002 The frame counter (FC) will start to count up from 0x0 when FCENB = 1, and add 1 when a frame is updated. When Version 2.0 SONiX TECHNOLOGY CO., LTD Page 196...

  • Page 197: Lcd Raw Interrupt Status Register (Lcd_Ris)

    SEG5 data for COM0~COM3 19:16 SEG4[3:0] SEG4 data for COM0~COM3 15:12 SEG3[3:0] SEG3 data for COM0~COM3 11:8 SEG2[3:0] SEG2 data for COM0~COM3 SEG1[3:0] SEG1 data for COM0~COM3 SEG0[3:0] SEG0 data for COM0~COM3 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 197...

  • Page 198: Lcd Seg Memory Register 1 (Lcd_Segm1)

    SEG17 data for COM0~COM3 SEG16[3:0] SEG16 data for COM0~COM3 16.9.10 LCD SEG Memory register 3 (LCD_SEGM3) Address Offset: 0x2C Reset value: 0x0000 0000 Name Description Attribute Reset 31:28 SEG31[3:0] SEG31 data for COM0~COM3 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 198...
  • Page 199 SEG29 data for COM0~COM3 19:16 SEG28[3:0] SEG28 data for COM0~COM3 15:12 SEG27[3:0] SEG27 data for COM0~COM3 11:8 SEG26[3:0] SEG26 data for COM0~COM3 SEG25[3:0] SEG25 data for COM0~COM3 SEG24[3:0] SEG24 data for COM0~COM3 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 199...

  • Page 200: Flash

    The FLASH memory may be programmed via the SONiX 32-bit MCU programming interface or by application code for maximum flexibility. SONiX 32-bit MCU provides security options at the disposal of the designer to prevent unauthorized access to information stored in FLASH memory.

  • Page 201: Organization

    17.7 EMBEDDED BOOT LOADER The embedded boot loader is used to reprogram the Flash memory using the USART0 serial interface. This program is located in the Boot ROM and is programmed by SONiX during production. Version 2.0 SONiX TECHNOLOGY CO., LTD...

  • Page 202: Flash Memory Controller (Fmc)

    1. Mass erase the User ROM first. User shall NOT execute this operation in debug mode, since the SWD communication may fail during the mass erase procedure. 2. Update security level. includes: - New option byte programming includes: - Option byte erase - Mass Erase Version 2.0 SONiX TECHNOLOGY CO., LTD Page 202...

  • Page 203: Program Flash Memory

    HW before reprogramming the read protection option. 17.10 HW CHECKSUM HW checksum is the checksum of User ROM. If the read protection is enabled, the users can still readout the HW checksum through Writer or ISP AP. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 203...

  • Page 204: Fmc Registers

    Note: HCLK MUST be equal to 12MHz during Flash program and erase operations. Name Description Attribute Reset 31:7 Reserved Checksum calculation chosen This bit is set only by SW and reset when the BUSY bit resets. Start Erase operation STARTE Version 2.0 SONiX TECHNOLOGY CO., LTD Page 204...

  • Page 205: Flash Data Register (Flash_Data)

    Choose the Flash address to erase when Page Erase is selected, or to program when Page Program is selected. 17.11.6 Flash Checksum register (FLASH_CHKSUM) Address offset: 0x14 Name Description Attribute Reset 31:16 Reserved 15:0 CHKSUM[15:0] Checksum of User ROM. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 205...

  • Page 206: Serial-Wire Debug (Swd)

    FW any more. SONiX provide Boot loader to check the status of P2.2 (BOOT pin) during boot procedure. If P2.2 is Low during Boot procedure, MCU will execute code in Boot loader instead of User code, so SWD function is not disabled.

  • Page 207: Internal Pull-Up/Down Resistors On Swd Pins

    To avoid any uncontrolled IO levels, the device embeds internal pull-up and pull-down resistor on the SWD input pins:  NJTRST: Internal pull-up  SWDIO/JTMS: Internal pull-up  SWCLK/JTCK: Internal pull-down Once a SWD function is disabled by SW, the GPIO controller takes control again. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 207...

  • Page 208: Development Tool

    SN32F760 Series 32-Bit Cortex-M0 Micro-Controller DEVELOPMENT TOOL SONiX provides an Embedded ICE emulator system to offer 32-bit series MCU firmware development. SONiX 32-bit series Embedded ICE Emulator System includes:  SONiX 32-bit MCU Starter-Kit.  SN-LINK-V3  USB cable to provide communications between the SN-LINK-V3 and PC.

  • Page 209: Sn-Link-V3

    32-Bit Cortex-M0 Micro-Controller 19.1 SN-LINK-V3 SN-LINK-V3 is a high speed emulator for SONiX 32-bit MCU. It debugs and programs based on SWD protocol. In addition to debugger functions, the SN-LINK-V3 also may be used as a programmer to load firmware from PC to MCU for engineering production, even mass production.

  • Page 210: Sn32F760 Starter-Kit

    19.2 SN32F760 STARTER-KIT SONiX 32-bit MCU Starter-kit is an easy-development platform. It includes real chip and I/O connectors to input signal or drive extra device of user’s application. It is a simple platform to develop application as target board not ready. The starter-kit can be replaced by target board because of integrated SWD debugger circuitry.
  • Page 211 P1.0~P1.5 & P0.10~P0.15 are GPIO pins, and connect VDD2 with VDD.  Short P0.0~P0.7 are LCD SEGx pins  JP22 Short Open P0.0~P0.7 are GPIO pins, and connect VDD3 with VDD with VDD. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 211...

  • Page 212: Electrical Characteristic

    I/O Low-level output sink current = Vss + 0.5V Typical 20mA mode ADC Operating Voltage AIN0 ~ AIN13 input voltage Avrefh ADC reference Voltage Ready to start convert after set ADENB = “1” *ADC enable time Version 2.0 SONiX TECHNOLOGY CO., LTD Page 212...
  • Page 213 [8] VDD is the Vddio of P0.8~P0.9, P2.0~P2.15, and P3.10~P3.15; VDD1 is the Vddio of P1.6~P1.15, and P3.0~P3.9; VDD2 is the Vddio of P1.0~P1.5, and P0.10~P0.15; VDD3 is the Vddio of P0.0~P0.7. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 213...

  • Page 214: Characteristic Graphs

    The Graphs in this section are for design guidance, not tested or guaranteed. In some graphs, the data presented are outside specified operating range. This is for information only and devices are guaranteed to operate properly only within the specified range. Version 2.0 SONiX TECHNOLOGY CO., LTD Page 214...
  • Page 215 SN32F760 Series 32-Bit Cortex-M0 Micro-Controller Supply Current V.S. Operating Temperature (Operating Conditions: All pins configured as GPIO outputs driven Low and pull-up resistors disabled and VDD = 3.3V) Version 2.0 SONiX TECHNOLOGY CO., LTD Page 215...

  • Page 216: Flash Rom Programming Pin

    Flash IC / JP3 Pin Assignment Connector Number Name Number Number Number Number Number P3.12 P3.12 P3.12 P3.12 P3.12 P0.8 P0.8 P0.8 P0.8 P0.8 P0.9 P0.9 P0.9 P0.9 P0.9 ALSB/PDB P3.11 P3.11 P3.11 P3.11 P3.11 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 216...

  • Page 217: Package Information

    SN32F760 Series 32-Bit Cortex-M0 Micro-Controller PACKAGE INFORMATION 22.1 LQFP 80 PIN Version 2.0 SONiX TECHNOLOGY CO., LTD Page 217...

  • Page 218: Lqfp 64 Pin

    SN32F760 Series 32-Bit Cortex-M0 Micro-Controller 22.2 LQFP 64 PIN Version 2.0 SONiX TECHNOLOGY CO., LTD Page 218...

  • Page 219: Lqfp 48 Pin

    SN32F760 Series 32-Bit Cortex-M0 Micro-Controller 22.3 LQFP 48 PIN SYMBOLS (mm) 0.05 0.15 1.35 1.45 0.09 0.16 9.00 BSC 7.00 BSC 9.00 BSC 7.00 BSC 0.5 BSC 0.17 0.27 0.45 0.75 1 REF Version 2.0 SONiX TECHNOLOGY CO., LTD Page 219...

  • Page 220: Qfn 46 Pin

    SN32F760 Series 32-Bit Cortex-M0 Micro-Controller 22.4 QFN 46 PIN Version 2.0 SONiX TECHNOLOGY CO., LTD Page 220...

  • Page 221: Qfn 33 Pin 5 5

    SN32F760 Series 32-Bit Cortex-M0 Micro-Controller 22.5 QFN 33 PIN 5x5 Version 2.0 SONiX TECHNOLOGY CO., LTD Page 221...

  • Page 222: Marking Definition

    SN32F760 Series 32-Bit Cortex-M0 Micro-Controller MARKING DEFINITION 23.1 INTRODUCTION There are many different types in SONiX 32-bit MCU production line. This note lists the marking definitions of all 32-bit MCU for order or obtaining information. 23.2 MARKING INDETIFICATION SYSTEM SN32 X Part No.

  • Page 223: Marking Example

    SN32F759FG Flash memory LQFP Green Package SN32F758FG -40℃~85℃ Flash memory LQFP Green Package -40℃~85℃ SN32F757FG Flash memory LQFP Green Package SN32F756JG Flash memory -40℃~85℃ Green Package -40℃~85℃ SN32F755JG Flash memory Green Package Version 2.0 SONiX TECHNOLOGY CO., LTD Page 223...

  • Page 224: Datecode System

    ..9=09 A=10 B=11 ..1=January Month 2=February ..9=September A=October B=November C=December 03= 2003 Year 04= 2004 05= 2005 06= 2006 ..Version 2.0 SONiX TECHNOLOGY CO., LTD Page 224...
  • Page 225 SONIX product could create a situation where personal injury or death may occur.

This manual is also suitable for:

Sn32f767Sn32f759Sn32f768Sn32f757Sn32f766Sn32f756 ... Show all

Table of Contents