1. Manuals
  2. Brands
  3. SONIX Manuals
  4. Microcontrollers
  5. SN32F260 Series
  6. User manual

SONIX SN32F260 Series User Manual

32-bit cortex-m0 micro-controller
Hide thumbs
Table of Contents

Advertisement

Quick Links

SN32F260 Series
USER'S MANUAL
SN32F268/267/265/264/2641/263
S
O
N
i
X
S
O
N
i
X
SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.
SONiX TECHNOLOGY CO., LTD
3
2
-
B
i
t
C
o
3
2
-
B
i
t
C
o
r
t
e
x
-
M
0
M
r
t
e
x
-
M
0
M
Page 1
SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
i
c
r
o
-
C
o
n
i
c
r
o
-
C
o
n
Version 1.5
t
r
o
l
l
e
r
t
r
o
l
l
e
r

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the SN32F260 Series and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for SONIX SN32F260 Series

Summary of Contents for SONIX SN32F260 Series

  • Page 1 SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur.

  • Page 2: Amendent History

    1. Add Note for setting the pins which are not pin-out. 2017/12/26 2. Modify typing error (CODE OPTION TABLE) 1. Modify DP/DN naming rule. 2018/09/19 2. Modify typing error of CT16Bn Register. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 2...

  • Page 3: Table Of Contents

    APPLICATION INTERRUPT AND RESET CONTROL (AIRC) ..........29 CODE OPTION TABLE ........................30 CORE REGISTER OVERVIEW ..................... 31 SYSTEM CONTROL..........................32 RESET .............................. 32 3.1.1 POWER-ON RESET (POR) ...................... 32 3.1.2 WATCHDOG RESET (WDT RESET) ..................33 Version 1.5 SONiX TECHNOLOGY CO., LTD Page 3...
  • Page 4 AHB Clock Enable register (SYS1_AHBCLKEN) ..............46 3.4.2 APB Clock Prescale register 1 (SYS1_APBCP1) ..............47 SYSTEM OPERATION MODE ......................48 OVERVIEW ............................. 48 NORMAL MODE ..........................48 LOW-POWER MODES ........................48 4.3.1 SLEEP MODE .......................... 48 Version 1.5 SONiX TECHNOLOGY CO., LTD Page 4...
  • Page 5 CT16Bn Timer Control register (CT16Bn_TMRCTRL) (n=0,1) ..........64 6.7.2 CT16Bn Timer Counter register (CT16Bn_TC) (n=0,1) ............64 6.7.3 CT16Bn Prescale register (CT16Bn_PRE) (n=0,1) ..............64 6.7.4 CT16Bn Prescale Counter register (CT16Bn_PC) (n=0,1) ............. 65 Version 1.5 SONiX TECHNOLOGY CO., LTD Page 5...
  • Page 6 SINGLE-FRAME ......................... 90 8.4.2.2 MULTI-FRAME ........................91 AUTO-SEL ............................91 SPI REGISTERS ..........................92 8.6.1 SPI n Control register 0 (SPIn_CTRL0) (n=0) ................ 92 8.6.2 SPI n Control register 1 (SPIn_CTRL1) (n=0) ................ 93 Version 1.5 SONiX TECHNOLOGY CO., LTD Page 6...
  • Page 7 FEATURES ............................ 104 10.3 PIN DESCRIPTION ........................104 10.4 BLOCK DIAGRAM ........................105 10.5 USB SRAM ACCESS ........................105 10.6 USB MACHINE ..........................106 10.7 USB INTERRUPT .......................... 106 10.8 USB ENUMERATION ........................107 Version 1.5 SONiX TECHNOLOGY CO., LTD Page 7...
  • Page 8 PROGRAM FLASH MEMORY ....................121 11.8.3 ERASE ............................ 121 11.8.3.1 PAGE ERASE ........................ 121 11.8.3.2 MASS ERASE ........................ 121 11.9 READ PROTECTION ........................121 11.10 HW CHECKSUM........................121 11.11 FMC REGISTERS ........................122 Version 1.5 SONiX TECHNOLOGY CO., LTD Page 8...
  • Page 9 QFN 33 PIN ............................ 136 16.7 SSOP 24 PIN ........................... 137 MARKING DEFINITION ....................... 138 17.1 INTRODUCTION .......................... 138 17.2 MARKING INDETIFICATION SYSTEM ..................138 17.3 MARKING EXAMPLE ......................... 139 17.4 DATECODE SYSTEM ........................140 Version 1.5 SONiX TECHNOLOGY CO., LTD Page 9...

  • Page 10: Product Overview

    QFN33 pin One control EP and 4 configurable INT/BULK QFN28 pin Endpoints. SOP28/SSOP28 pin EP0 supports 64-byte FIFO depth. SSOP24 pin Programmable EP1~EP4 FIFO depth. Total 5 endpoints share 256-byte USB RAM. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 10...
  • Page 11 48 MHz 16-bitx2 22-CH QFN46 SN32F265J 32KB 48 MHz 16-bitx2 17-CH QFN33 SN32F2641J 32KB 48 MHz 16-bitx2 13-CH QFN28 SN32F264S/X 32KB 48 MHz 16-bitx2 11-CH SOP28/SSOP28 SN32F263X 32KB 48 MHz 16-bitx2 11-CH SSOP24 Version 1.5 SONiX TECHNOLOGY CO., LTD Page 11...

  • Page 12: System Block Diagram

    Controls BRIDGE /RESET SYSTEM FUNCTIONS ILRC IHRC 32KHz 48MHz GPIO0_0~15 SCK0 SPI0 GPIO1_0~5 SDI0 GPIO GPIO2 0~10 SDO0 GPIO3 0~8 CT16B1_PWM[22:21]/ 16-bit TIMER 1 16-bit TIMER 0 CT16B1_PWM[[19:0] with 22 PWM CT16B0_CAP0 Version 1.5 SONiX TECHNOLOGY CO., LTD Page 12...

  • Page 13: Clock Generation Block Diagram

    USB_PCLK = 48MHz clock source register block AHB clock for GPIOn USBCLKEN GPIOn block AHB clock for USB GPIOnCLKEN n=0,1,2,3 AHB clock for SRAM SRAM block AHB clock for FLASH FLASH block Version 1.5 SONiX TECHNOLOGY CO., LTD Page 13...

  • Page 14: Pin Assignment

    P0.0/CT16B1_PWM0/CLKOUT P2.7 P0.1/CT16B1_PWM1 P2.6 P0.2/CT16B1_PWM2 P2.5 SN32F268F P0.3/CT16B1_PWM3 P2.4 P0.4/CT16B1_PWM4/SCL0 P2.3 P0.5/CT16B1_PWM5/SDA0 P3.8/RESET/CT16B1_PWM22 P0.6/CT16B1_PWM6 P3.7/SWDIO P0.7/CT16B1_PWM7 P3.6/SWCLK P0.8/CT16B1_PWM8 P3.5 CT16B1_PWM21 13 14 15 16 17 18 19 20 21 22 23 24 Version 1.5 SONiX TECHNOLOGY CO., LTD Page 14...
  • Page 15 10 11 12 13 14 15 16 17 18 19 20 21 22 23  Note: The pins which are not pin-out shall be set correctly to decrease power consumption in low- power modes. Strongly recommended to set these pins as input pull-up. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 15...
  • Page 16 10 11 12 13 14 15 16  Note: The pins which are not pin-out shall be set correctly to decrease power consumption in low- power modes. Strongly recommended to set these pins as input pull-up. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 16...
  • Page 17 P3.4 P0.4/CT16B1_PWM4/SCL0 P3.3/CT16B1_PWM19  Note: The pins which are not pin-out shall be set correctly to decrease power consumption in low- power modes. Strongly recommended to set these pins as input pull-up. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 17...
  • Page 18 P0.12/CT16B1_PWM12 P0.11/CT16B1_PWM11 SN32F263X  Note: The pins which are not pin-out shall be set correctly to decrease power consumption in low- power modes. Strongly recommended to set these pins as input pull-up. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 18...

  • Page 19: Pin Descriptions

    SEL0 — Slave Select for SPI. P1.3 — General purpose digital input/output pin. P1.3/SCK0 SCK0 — Serial clock for SPI. P1.4 — General purpose digital input/output pin. P1.4/MISO0 MISO0 — Master In Slave Out for SPI. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 19...
  • Page 20 SWDIO — Serial Wire Data input/output pin. P3.8 — General purpose digital input/output pin. RESET — External Reset input. Schmitt trigger structure, active “Low”, normally P3.8/RESET/CT16B1 stay “High”. _PWM22 CT16B1_PWM22 — PWM output 22 for CT16B1. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 20...

  • Page 21: Pin Circuit Diagrams

    GPIOn_CFG GPIOPn_MODE Output Bus Output Latch Specific Output Bus *. Specific Output Function Control Bit Specific Input Function Control Bit *. Some specific functions switch I/O direction directly, not through GPIOn_MODE register. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 21...

  • Page 22: Central Processor Unit (Cpu)

    0x4001 6000 Reserved 0x4001 4000 Reserved 0x4001 2000 0x0000 8000 0x4001 0000 Reserved 32 KB on-chip Flash 0x4000 C000 Reserved 0x4000 A000 Reserved 0x0000 0000 0x4000 4000 CT16B1 0x4000 2000 CT16B0 0x4000 0000 Version 1.5 SONiX TECHNOLOGY CO., LTD Page 22...

  • Page 23: System Tick Timer

    When the counter transitions to zero, the COUNTFLAG status bit is set to 1. The COUNTFLAG bit clears on reads.  Note: When the processor is halted for debugging the counter does not decrease. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 23...

  • Page 24: Systick Usage Hints And Tips

    RELOAD = (system tick clock frequency × 10 ms) −1 = (48 MHz × 10 ms) −1 = 0x000752FF. Name Description Attribute Reset 31:24 Reserved Value to load into the SYSTICK_VAL when the counter is enabled and 23:0 RELOAD 0x5F7F9B when it reaches 0. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 24...

  • Page 25: System Tick Timer Current Value Register (Systick_Val)

    1: TENMS value is inexact, or not given. 29:24 Reserved Reload value for 10ms timing, subject to system clock skew errors. If the 23:0 TENMS 0xA71FF value reads as zero, the calibration value is not known. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 25...

  • Page 26: Nested Vectored Interrupt Controller (Nvic)

    IRQ7/ 0x0000 005C Settable IRQ8/ 0x0000 0060 Settable IRQ9/ 0x0000 0064 Settable IRQ10/ 0x0000 0068 Settable IRQ11/ 0x0000 006C Settable IRQ12/ 0x0000 0070 Settable IRQ13/SPI0IRQ SPI0 0x0000 0074 Settable IRQ14/ 0x0000 0078 Version 1.5 SONiX TECHNOLOGY CO., LTD Page 26...

  • Page 27: Nvic Registers

    Address: 0xE000 E180 (Refer to Cortex-M0 Spec.) The ICER disables interrupts, and shows the interrupts that are enabled. Name Description Attribute Reset Interrupt clear-enable bits. 31:0 CLRENA[31:0] Write 0: No effect 1: Disable interrupt. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 27...

  • Page 28: Irq0~31 Interrupt Set-Pending Register (Nvic_Ispr)

    The processor implements only bits[23:22] of each field, bits [21:16] read as zero and ignore writes. This means writing 255 to a priority register saves value 192 to the register. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 28...

  • Page 29: Application Interrupt And Reset Control (Airc)

    1: Requests a system level reset. Reserved for debug use. This bit read as 0. When writing to the register VECTCLRACTIVE you must write 0 to this bit, otherwise behavior is Unpredictable. Reserved Version 1.5 SONiX TECHNOLOGY CO., LTD Page 29...

  • Page 30: Code Option Table

    32-Bit Cortex-M0 Micro-Controller 2.5 CODE OPTION TABLE Address: 0x1FFF 2000 Name Description Attribute Reset 31:16 Code Security[15:0] Code Security 0000 0x0000: CS0 0x5A5A: CS1 0xA5A5: CS2 Other: CS2 15:0 Reserved All 0 Bit[1]=1 Version 1.5 SONiX TECHNOLOGY CO., LTD Page 30...

  • Page 31: Core Register Overview

    These registers are mutually exclusive bit fields in the 32-bit PSR. The PRIMASK register prevents activation of all exceptions with configurable priority. PRIMASK The CONTROL register controls the stack used when the processor is in Thread mode. CONTROL Version 1.5 SONiX TECHNOLOGY CO., LTD Page 31...

  • Page 32: System Control

    System initialization: All system registers is set as initial conditions and system is ready.  Oscillator warm up: Oscillator operation is successfully and supply to system clock.  Program executing: Power on sequence is finished and program executes from Boot loader. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 32...

  • Page 33: Watchdog Reset (Wdt Reset)

    V1 doesn’t touch the below area and not affect the system operation. But the V2 and V3 is under the below area and may induce the system error occurrence. Let system under dead-band includes some conditions. DC application: Version 1.5 SONiX TECHNOLOGY CO., LTD Page 33...

  • Page 34: The System Operating Voltage Decsription

    External reset circuit. (Zener diode reset circuit, Voltage bias reset circuit, External reset IC)  Note: The “Zener diode reset circuit”, “Voltage bias reset circuit” and “External reset IC” can completely improve the brown out reset, DC low battery and AC slow power down conditions. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 34...

  • Page 35: External Reset

    Delay Time The LVD (low voltage detector) is built-in SONiX 32-bit MCU to be brown out reset protection. When the VDD drops and is below LVD detect voltage, the LVD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt;...

  • Page 36: Simply Rc Reset Circuit

    DIODE & RC RESET CIRCUIT DIODE 47K ohm 100 ohm 0.1uF This is the better reset circuit. The R1 and C1 circuit operation is like the simply reset circuit to make a power on signal. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 36...

  • Page 37: Zener Diode Reset Circuit

    Select the right Zener voltage to conform the application. 3.1.4.4 VOLTAGE BIAS RESET CIRCUIT 47K ohm 10K ohm 2K ohm The voltage bias reset circuit is a low cost voltage detector and can improve brown out reset condition completely. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 37...

  • Page 38: External Reset Ic

    The internal reset is deasserted and the MCU loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 38...

  • Page 39: System Clock

    RC type oscillator circuit. The frequency is affected by the voltage and temperature of the system. In common condition, the frequency of the RC oscillator is about 32 KHz.  Note: The ILRC can ONLY be switched on and off by HW. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 39...

  • Page 40: System Clock (Sysclk) Selection

    GPIO port must be programmed in alternate function mode. One of 3 clock signals can be selected as clock output: HCLK IHRC ILRC The selection is controlled by the CLKOUTSEL bits in SYS1_AHBCLKEN register. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 40...

  • Page 41: System Control Registers 0

    Set and cleared by HW to indicate which clock source is used as system clock. 000: IHRC is used as system clock 001: ILRC is used as system clock Other: Reserved Reserved System clock switch SYSCLKSEL[2:0] Set and cleared by SW. 000: IHRC 001: ILRC Version 1.5 SONiX TECHNOLOGY CO., LTD Page 41...

  • Page 42: Ahb Clock Prescale Register (Sys0_Ahbcp)

    0: ReadNo watchdog reset occurred WriteClear this bit 1: Watchdog reset occurred. Software reset flag SWRSTF Set by HW when a software reset occurs. 0: ReadNo software reset occurred WriteClear this bit 1: Software reset occurred. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 42...

  • Page 43: Lvd Control Register (Sys0_Lvdctrl)

    Attribute Reset 31:1 Reserved SWD pin disable bit. SWDDIS 0: Enable SWD pin. (P3.7 acts as SWDIO pin, P3.6 acts as SWCLK pin) 1: Disable. (P3.7 and P3.6 act as GPIO pins) Version 1.5 SONiX TECHNOLOGY CO., LTD Page 43...

  • Page 44: Interrupt Vector Table Mapping Register (Sys0_Ivtm)

    NDT5V_DET 1: Power noise is detected by NDT5V IP. *Cleared by write 1 to SYS0_NDTSTS[1] Reserved 3.3.12 Anti-EFT Ability Control register (SYS0_ANTIEFT) Address Offset: 0x30 This register decides the HW anti-EFT ability. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 44...
  • Page 45 SN32F260 Series 32-Bit Cortex-M0 Micro-Controller Name Description Attribute Reset 31:3 Reserved HW anti-EFT ability. AEFT[2:0] 000: No 010: Low 011: Medium 100: Strong Version 1.5 SONiX TECHNOLOGY CO., LTD Page 45...

  • Page 46: System Control Registers 1

    Enables clock for P3. P3CLKEN 0: Disable 1: Enable Enables clock for P2. P2CLKEN 0: Disable 1: Enable Enables clock for P1. P1CLKEN 0: Disable 1: Enable Enables clock for P0. P0CLKEN Version 1.5 SONiX TECHNOLOGY CO., LTD Page 46...

  • Page 47: Apb Clock Prescale Register 1 (Sys1_Apbcp1)

    SysTick clock source prescaler 17:16 SYSTICKPRE[1:0] 00: SysTick_PCLK = HCLK / 1. 01: SysTick_PCLK = HCLK / 2. 10: SysTick_PCLK = HCLK / 4. 11: SysTick_PCLK = HCLK / 8. 15:0 Reserved Version 1.5 SONiX TECHNOLOGY CO., LTD Page 47...

  • Page 48: System Operation Mode

    The power state of the analog blocks (IHRC, Flash, and LVD) is determined by the enable bit of all blocks. The processor state and registers, peripheral registers, and internal SRAM values are maintained and the logic levels of the pins remain static. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 48...

  • Page 49: Deep-Sleep Mode

    Sleep mode, MCU waits for 2048 external high-speed oscillator clocks and 32 internal high-speed oscillator clocks as the wakeup time to stable the oscillator circuit. After the wakeup time, the system goes into the Version 1.5 SONiX TECHNOLOGY CO., LTD Page 49...

  • Page 50: State Machine Of Pmu

    One of reset trigger sources actives Sleep mode mode Wake-up condition Interrupt Wake-up condition GPIO0/1 Enter mode condition 1. PMU_CTRL = 2 2. WFI instruction Reset condition One of reset trigger sources actives Deep-sleep mode Version 1.5 SONiX TECHNOLOGY CO., LTD Page 50...

  • Page 51: Operation Mode Comparsion Table

    By USBEN By USBEN Disable Peripherals By Enable bit of each peripherals Disable HCLK IO status Output Low Output Low Output Low GPIO0/1/2/3 interrupt, Wakeup Source All interrupts, RESET pin RESET pin Version 1.5 SONiX TECHNOLOGY CO., LTD Page 51...

  • Page 52: Pmu Registers

    Deep-sleep mode) is entered and provides the flags for Sleep or Deep-sleep modes respectively. Name Description Attribute Reset 31:3 Reserved Low power mode selection MODE[2:0] 010: WFI instruction will make MCU enter Deep-sleep mode. 100: WFI instruction will make MCU enter Sleep mode. Other: Disable Version 1.5 SONiX TECHNOLOGY CO., LTD Page 52...

  • Page 53: General Purpose I/O Port (Gpio)

    Schmitt trigger disabled mode The possible on-chip resistor configurations are pull-up enabled, no pull-up/pull-down with Schmitt trigger enabled (default), or no pull-up/pull-down with Schmitt trigger disabled. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 53...

  • Page 54: Gpio Registers

    Configuration of Pn.15 31:30 CFG15[1:0] 00: Pull-up resistor enabled. 01: Reserved. Schmitt 10: Inactive. (no pull-up resistor enabled, trigger enabled). Schmitt 11: Inactive. (no pull-up resistor enabled, trigger disabled, Data register keep low) Version 1.5 SONiX TECHNOLOGY CO., LTD Page 54...
  • Page 55 Configuration of Pn.4 CFG4[1:0] 00: Pull-up resistor enabled. 01: Reserved. Schmitt 10: Inactive. (no pull-up resistor enabled, trigger enabled). Schmitt 11: Inactive. (no pull-up resistor enabled, trigger disabled, Data Version 1.5 SONiX TECHNOLOGY CO., LTD Page 55...

  • Page 56: Gpio Port N Interrupt Sense Register (Gpion_Is) (N=0,1,2,3)

    Selects interrupt on pin x to be triggered rising or falling edges. (x = 0 to 15) 15:0 IEV[15:0] 0: Depending on setting in register GPIOn_IS, Rising edges or HIGH level on Pn.x trigger an interrupt. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 56...

  • Page 57: Gpio Port N Interrupt Enable Register (Gpion_Ie) (N=0,1,2,3)

    GPIOn_BSET register is set. Name Description Attribute Reset 31:16 Reserved Bit Set enable. (x = 0 to 15) 15:0 BSET[15:0] 0: No effect on Pn.x. 1: Set Pn.x to “1”. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 57...

  • Page 58: Gpio Port N Bits Clear Operation Register (Gpion_Bclr) (N=0,1,2,3)

    Name Description Attribute Reset 31:16 Reserved Bit clear enable. (x = 0 to 15) 15:0 BCLR[15:0] 0: No effect on Pn.x. 1: Clear Pn.x. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 58...

  • Page 59: 16-Bit Timer0 With Capture Function

    – Toggle on match. – Do nothing on match. 6.3 PIN DESCRIPTION Pin Name Type Description GPIO Configuration CT16Bn_CAP0 Capture channel input 0. Depends on GPIOn_CFG CT16Bn_PWMx Output channel x of Match/PWM output. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 59...

  • Page 60: Block Diagram

    6.4 BLOCK DIAGRAM MRxSTOP CRST CRST MRxIF STOP STOP MRxIE MRx Interrupt PCLK MRxRST RESET RESET PWMxEN PWMxMODE CT16Bn_PWMx PWMxIOEN PWMxNIOEN PWMxNDB CT16Bn_PWMxN EMCx CAP0 CAP0EN CT16Bn_CAP0 CAP0FE CAP0IE CAP0 Interrupt CAP0IE CAP0RE Version 1.5 SONiX TECHNOLOGY CO., LTD Page 60...

  • Page 61: Timer Operation

    6. In the next clock after the timer reaches the match value, the CEN bit in CT16Bn_TMRCTRL register is cleared, and the interrupt indicating that a match occurred is generated. PCLK CT16Bn_PC CT16Bn_TC CEN bit Interrupt Version 1.5 SONiX TECHNOLOGY CO., LTD Page 61...

  • Page 62: Pwm

    PWM cycle length. For this register, set the MRnR bit to one to enable the timer reset when the timer value matches the value of the corresponding match register. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 62...

  • Page 63: Pwm Mode 2

    PWM cycle length. For this register, set the MRnR bit to one to enable the timer reset when the timer value matches the value of the corresponding match register. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 63...

  • Page 64: Ct16B Nregisters

    0x00000000. This event does not cause an interrupt, but a Match register can be used to detect an overflow if needed. Name Description Attribute Reset 31:16 Reserved 15:0 TC[15:0] Timer Counter. 6.7.3 CT16Bn Prescale register (CT16Bn_PRE) (n=0,1) Address Offset: 0x08 Name Description Attribute Reset 31:8 Reserved PRE[7:0] Prescale max value. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 64...

  • Page 65: Ct16Bn Prescale Counter Register (Ct16Bn_Pc) (N=0,1)

    10: Counter Mode: TC is incremented on falling edges on the CAP0 input selected by CIS bits. 11: Counter Mode: TC is incremented on both edges on the CAP0 input selected by CIS bits. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 65...

  • Page 66: Ct16Bn Match Control Register (Ct16Bn_Mctrl) (N=0)

    Enable generating an interrupt based on CM[2:0] when MR7 matches the MR7IE value in the TC. 0: Disable. 1: Enable. Stop MR6: TC and PC will stop and CEN bit will be cleared if MR6 MR6STOP matches TC. 0: Disable. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 66...
  • Page 67 Enable generating an interrupt based on CM[2:0] when MR1 matches the MR1IE value in the TC. 0: Disable. 1: Enable. Stop MR0: TC and PC will stop and CEN bit will be cleared if MR0 MR0STOP matches TC. 0: Disable. 1: Enable. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 67...

  • Page 68: Ct16Bn Match Control Register 2(Ct16Bn_Mctrl2) (N=1)

    Enable generating an interrupt based on CM[2:0] when MR16 matches the MR16IE value in the TC. 0: Disable. 1: Enable. Stop MR15: TC and PC will stop and CEN bit will be cleared if MR15 MR15STOP matches TC. 0: Disable. 1: Enable. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 68...
  • Page 69 Enable reset TC when MR10 matches TC. MR10RST 0: Disable. 1: Enable. Enable generating an interrupt based on CM[2:0] when MR10 matches the MR10IE value in the TC. 0: Disable. 1: Enable. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 69...

  • Page 70: Ct16Bn Match Control Register 3 (Ct16Bn_Mctrl3) (N=1)

    Enable reset TC when MR21 matches TC. MR21RST 0: Disable. 1: Enable. Enable generating an interrupt based on CM[2:0] when MR21 matches the MR21IE value in the TC. 0: Disable. 1: Enable. Reserved Version 1.5 SONiX TECHNOLOGY CO., LTD Page 70...

  • Page 71: Ct16Bn Match Register 0 (Ct16Bn_Mr0) (N=0)

    0: Disable. 1: Enable. Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CAP0FE CT16Bn_CAP0 will cause CAP0 to be loaded with the contents of TC. 0: Disable. 1: Enable. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 71...

  • Page 72: Ct16Bn Capture 0 Register (Ct16Bn_Cap0) (N=0)

    When the TC and MR7 are equal, this bit will act according to EMC7 bits, and also drive the state of CT16Bn_PWM7 output. When the TC and MR6 are equal, this bit will act according to EMC6 bits, and also drive the state of CT16Bn_PWM6 output. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 72...

  • Page 73: Ct16Bn External Match Control Register (Ct16Bn_Emc)(N=1)

    00: Do Nothing. 01: CT16Bn_PWM8 pin is LOW. 10: CT16Bn_PWM8 pin is HIGH. 11: Toggle CT16Bn_PWM8 pin. Determines the functionality of CT16Bn_PWM7. 15:14 EMC7[1:0] 00: Do Nothing. 01: CT16Bn_PWM7 pin is LOW. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 73...

  • Page 74: Ct16Bn External Match Control Register 2(Ct16Bn_Emc2)(N=1)

    10: CT16Bn_PWM21 pin is HIGH. 11: Toggle CT16Bn_PWM21 pin. Reserved Determines the functionality of CT16Bn_PWM19. EMC19[1:0] 00: Do Nothing. 01: CT16Bn_PWM19 pin is LOW. 10: CT16Bn_PWM19 pin is HIGH. 11: Toggle CT16Bn_PWM19 pin. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 74...

  • Page 75: Ct16Bn Pwm Control Register (Ct16Bn_Pwmctrl) (N=1)

    10: PWM12 is forced to 0. 11: PWM12 is forced to 1. PWM11 output. 23:22 PWM11MODE[1:0] 00: PWM mode 1. PWM11 is 0 when TC<MR11 during Up-counting period. 01: PWM mode 2. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 75...
  • Page 76 PWM2 is 0 when TC<MR2 during Up-counting period. 01: PWM mode 2. PWM2 is 1 when TC<MR2 during Up-counting period. 10: PWM2 is forced to 0. 11: PWM2 is forced to 1. PWM1 output. PWM1MODE[1:0] 00: PWM mode 1. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 76...

  • Page 77: Ct16Bn Pwm Control Register 2 (Ct16Bn_Pwmctrl2) (N=1)

    PWM18 is 1 when TC<MR18 during Up-counting period. 10: PWM18 is forced to 0. 11: PWM18 is forced to 1. PWM17 output. PWM17MODE[1:0] 00: PWM mode 1. PWM17 is 0 when TC<MR17 during Up-counting period. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 77...

  • Page 78: Ct16Bn Pwm Enable Register (Ct16Bn_Pwmenb) (N=1)

    PWM12 enable. PWM12EN 0: CT16Bn_PWM12 is controlled by EM12. 1: PWM mode is enabled for CT16Bn_PWM12. PWM11 enable. PWM11EN 0: CT16Bn_PWM11 is controlled by EM11. 1: PWM mode is enabled for CT16Bn_PWM11. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 78...

  • Page 79: Pwm Io Enable Register (Ct16Bn_Pwmioenb) (N=1 )

    1: CT16Bn_PWM21 pin act as match output, and output signal depends on PWM21EN bit. Reserved CT16Bn_PWM19/GPIO selection bit. PWM19IOEN 0: CT16Bn_PWM19 pin act as GPIO. 1: CT16Bn_PWM19 pin act as match output, and output signal depends on PWM19EN bit. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 79...
  • Page 80 1: CT16Bn_PWM3 pin act as match output, and output signal depends on PWM3EN bit. CT16Bn_PWM2/GPIO selection bit. PWM2IOEN 0: CT16Bn_PWM2 pin act as GPIO. 1: CT16Bn_PWM2 pin act as match output, and output signal depends Version 1.5 SONiX TECHNOLOGY CO., LTD Page 80...

  • Page 81: Ct16Bn Timer Raw Interrupt Status Register (Ct16Bn_Ris) (N=0, 1)

    0: No interrupt on match channel 11. 1: Interrupt requirements met on match channel 11. Interrupt flag for match channel 10. MR10IF 0: No interrupt on match channel 10. 1: Interrupt requirements met on match channel 10. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 81...

  • Page 82: Ct16Bn Timer Interrupt Clear Register (Ct16Bn_Ic) (N=0,1)

    1: Clear MR15IF bit. 0: No effect. MR14IC 1: Clear MR14IF bit. 0: No effect. MR13IC 1: Clear MR13IF bit. 0: No effect. MR12IC 1: Clear MR12IF bit. 0: No effect. MR11IC Version 1.5 SONiX TECHNOLOGY CO., LTD Page 82...
  • Page 83 0: No effect. MR3IC 1: Clear MR3IF bit. 0: No effect. MR2IC 1: Clear MR2IF bit. 0: No effect. MR1IC 1: Clear MR1IF bit. 0: No effect. MR0IC 1: Clear MR0IF bit. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 83...

  • Page 84: Watchdog Timer (Wdt)

    The clock to the watchdog register block can be disabled in AHB Clock Enable register (SYS1_AHBCLKEN) register for power savings. Watchdog reset or interrupt will occur any time the watchdog is running and has an operating clock source. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 84...

  • Page 85: Block Diagram

    SN32F260 Series 32-Bit Cortex-M0 Micro-Controller 7.2 BLOCK DIAGRAM Feed Watchdog WDT_TC WDT_FEED Feed OK Reload Counter WDT_PCLK /128 8-bit Down Counter Enable Counter underflow WDT_CFG WDINT WDTIE WDTEN WDT Reset WDT Interrupt Version 1.5 SONiX TECHNOLOGY CO., LTD Page 85...

  • Page 86: Wdt Registers

    0000 0000 : Timer constant = 1 0000 0001 : Timer constant = 2 ………. ………. 1111 1110 : Timer constant = 255 1111 1111 : Timer constant = 256  Watchdog clock source is fixed as ILRC. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 86...

  • Page 87: Watchdog Feed Register (Wdt_Feed)

    WDKEY, otherwise behavior of writing to the register is ignored. Feed value (Read as 0x0) 15:0 FV[15:0] 0x55AA: The watchdog is fed, and the WDT_TC value is reloaded in the watchdog counter. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 87...

  • Page 88: Spi

    SPI Slave Select (Slave) Depends on GPIOn_CFG MISOn Master In Slave Out (Master) Depends on GPIOn_CFG Master In Slave Out (Slave) Master Out Slave In (Master) MOSIn Master Out Slave In (Slave) Depends on GPIOn_CFG Version 1.5 SONiX TECHNOLOGY CO., LTD Page 88...

  • Page 89: Interface Description

    SCK first edge is to receive and transmit data. The SPI data transfer timing as following figure: MLSB CPOL CPHA Idle Diagrams Status bit1 High bit1 bit1 Next data High bit1 Next data bit1 High bit1 bit1 Next data Version 1.5 SONiX TECHNOLOGY CO., LTD Page 89...

  • Page 90: Communication Flow

    SN32F260 Series 32-Bit Cortex-M0 Micro-Controller High bit1 Next data 8.4.2 COMMUNICATION FLOW 8.4.2.1 SINGLE-FRAME CPOL=0 CPHA=1 CPOL=1 CPHA=0 CPOL=1 CPHA=1 CPOL=0 CPHA=0 DATA DATA DX/DR Version 1.5 SONiX TECHNOLOGY CO., LTD Page 90...

  • Page 91: Multi-Frame

    If Auto-SEL function is disabled (SELDIS = 1), HW does NOT control SELn pin at all, SELn pin is GPIO. If Auto-SEL function is enabled (SELDIS = 0), SPI HW controls the SELn activity. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 91...

  • Page 92: Spi Registers

    Slave data output disable bit. (ONLY used in slave mode) SDODIS 0: Enable slave data output. 1: Disable slave data output. (MISO=0) Loop back mode enable. LOOPBACK 0: Disable. 1: Data input from data output. SPI enable bit. SSPEN 0: Disable. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 92...

  • Page 93: Spi N Control Register 1 (Spin_Ctrl1) (N=0)

    1: RX FIFO is full. RX FIFO empty flag. RX_EMPTY 0: RX FIFO is NOT empty. 1: RX FIFO is empty. TX FIFO full flag. TX_FULL 0: TX FIFO is NOT full. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 93...

  • Page 94: Spi N Interrupt Enable Register (Spin

    RXOVF occurs when the RX FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. 0: RXOVF doesn’t occur. 1: RXOVF occurs. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 94...

  • Page 95: Spi N Interrupt Clear Register (Spin

    0s. 8.6.9 SPI n Data Fetch register (SPIn _DF) (n=0) Address Offset: 0x20 Name Description Attribute Reset 31:1 Reserved SPI data fetch control bit. 0: Disable. 1: Enable. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 95...

  • Page 96: I2C

     Serial clock synchronization allows devices with different bit rates to communicate via one serial bus.  Serial clock synchronization is used as a handshake mechanism to suspend and resume serial transfer. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 96...

  • Page 97: Pin Description

    I2C Serial clock Output with Open-drain Input depends on GPIOn_CFG SDAn I2C Serial data Output with Open-drain Input depends on GPIOn_CFG 9.4 WAVE CHARACTERISTICS Data Data START STOP Change Change Signal Signal Allowed Allowed Version 1.5 SONiX TECHNOLOGY CO., LTD Page 97...

  • Page 98: I2C Master Modes

    “not acknowledge” to the bus. Arbitration is lost when another device on the bus pulls this signal low. Since this can occur only at the end of a serial byte, the I2C block generates no further clock pulses. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 98...

  • Page 99: I2C Slave Modes

    9.6 I2C SLAVE MODES 9.6.1 SLAVE TRANSMITTER MODE R/W=0 Receiving Address Transmission Data R/W=1 ACK_ ACK_ 9.6.2 SLAVE RECEIVER MODE Receiving Address Receiving Data Receiving Data R/W=0 ACK_ ACK_ ACK_ Terminate by Master Version 1.5 SONiX TECHNOLOGY CO., LTD Page 99...

  • Page 100: I2C Registers

    Assert ACK (Low level to SDA) flag. 0: Master mode No function. Slave modeReturn a NACK after receiving address or data. 1: An ACK will be returned during the acknowledge clock pulse on SCLn. when Version 1.5 SONiX TECHNOLOGY CO., LTD Page 100...

  • Page 101: I2C N Status Register (I2Cn_Stat) (N=0)

    0: No START bit. 1: MASTER mode a START bit was issued. SLAVE modea START bit was received. Stop done status. STOP_DN 0: No STOP bit. 1: MASTER modea STOP condition was issued. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 101...

  • Page 102: I2C N Tx Data Register (I2Cn_Txdata) (N=0)

    The I2C slave address. ADDR[9:0] ADD[9:0] is valid when ADD_MODE = 1. ADD[7:1] is valid when ADD_MODE = 0. 9.7.6 I2C n Slave Address 1~3 register (I2Cn_SLVADDR1~3) (n=0) Address Offset: 0x14, 0x18, 0x1C Version 1.5 SONiX TECHNOLOGY CO., LTD Page 102...

  • Page 103: I2C N Scl High Time Register (I2Cn_Sclht) (N=0)

    Time-out status will be cleared automatically by writing I2Cn_CTRL or I2Cn_TXDATA register. Name Description Attribute Reset 31:16 Reserved Count for checking Timeout. 15:0 TO[15:0] 0: Disable Timeout checking. N: Timeout period time = N*32*I2Cn_PCLK cycle. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 103...

  • Page 104: Usb Fs Device Interface

    The USB is the answer to connectivity for the PC architecture. A fast, bi-directional interrupt pipe, low-cost, dynamically attachable serial interface is consistent with the requirements of the PC platform of today and tomorrow. The SONIX USB microcontrollers are optimized for human-interface computer peripherals such as a mouse, keyboard, joystick, and game pad.

  • Page 105: Block Diagram

    USB SRAM start address (USB_SRAM) = USB_BA + 0x100 000h EP0 SRAM Buffer (64 bytes) 03Fh EP1BUFOS 040h EP1 SRAM Buffer (N bytes) EP2BUFOS ……… ………………………… ……… EPnBUFOS EPn SRAM Buffer (M bytes) 0FFh Version 1.5 SONiX TECHNOLOGY CO., LTD Page 105...

  • Page 106: Usb Machine

    The USB host sends USB suspend request to the device. – USB bus reset/resume event occurs. – The USB endpoints interrupt after a USB transaction complete is on the bus. – The NAK handshaking when the NAK interrupt enables. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 106...

  • Page 107: Usb Enumeration

    The host generates control reads from the device to request the Configuration and Report descriptors. 10. Once the device receives a Set Configuration request, its functions may now be used. 11. Firmware should take appropriate action for Endpoint 0~N transactions, which may occur from this point. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 107...

  • Page 108: Usb Registers

    0: Disable Wake Up event interrupt. 1: Enable Wake Up event interrupt. 27:5 Reserved Enable all of EP(1~4) ACK Interrupt EPN_ACK_EN 0: Disable EP1 to 4 ACK interrupt function. 1: Enable EP1 to 4 ACK interrupt function. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 108...

  • Page 109: Usb Interrupt Event Status Register (Usb_Insts)

    1: EP0 IN STALL transaction is completed. Cleared by write 1 to USB_INSTSC[20]. EP0 OUT STALL transaction flag. EP0_OUT_STALL 0: No EP0 OUT STALL transaction. 1: EP0 OUT STALL transaction is completed. Cleared by write 1 to USB_INSTSC[19]. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 109...

  • Page 110: Usb Interrupt Event Status Clear Register (Usb_Instsc)

    BUS_RESUMEC 1: Clear BUS_RESUME bit. 28:27 Reserved 0: No effect. USB_SOFC 1: Clear USB_SOF bit. Reserved 0: No effect EP0_PRESETUPC 1: Clear EP0_PRESETUP bit. 0: No effect EP0_SETUPC 1: Clear EP0_SETUP bit. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 110...

  • Page 111: Usb Device Address Register (Usb_Addr)

    0: Disable 1: Enable PHY transceiver function. PHY will be automatically disabled if entering PHY_EN sleep mode, deep-sleep mode, and deep-power down mode. 0: Disable PHY transceiver function. 1: Enable PHY transceiver function. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 111...

  • Page 112: Usb Signal Control Register (Usb_Sgctl)

    Address Offset: 0x18 Reset value: 0x0000 0000 Name Description Attribute Reset Enable Endpoint 0 function. ENDP_EN 0: Disable endpoint 0 function. No handshake to endpoint0 SETUP/IN/ OUT token. 1: Enable endpoint 0 function. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 112...

  • Page 113: Usb Endpoint N Control Register (Usb_Epnctl, N = 1 ~ 4)

    Endpoint Byte Count ENDP_CNT[6:0] For IN direction usage, the ENDP_CNT indicates the byte count to be uploaded to host. For OUT direction usage, the ENDP_CNT indicates the byte count received from host. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 113...

  • Page 114: Usb Endpoint Data Toggle Register (Usb_Eptoggle)

    The 11-bit frame number of the Start-Of-Frame(SOF) packet. This 10:0 FRAME_NO[10:0] number is updated by H/W automatically when SOF packet is received. 10.9.12 USB PHY Parameter Register (USB_PHYPRM) Address Offset: 0x64 Reset value: 0x0000 0000 Version 1.5 SONiX TECHNOLOGY CO., LTD Page 114...

  • Page 115: Usb Phy Parameter Register 2(Usb_Phyprm2)

    10.9.15 USB Read/Write Address Register (USB_RWADDR) Address Offset: 0x78 Reset value: 0x0000 0000 Name Description Attribute Reset 31:8 Reserved USB FIFO address to be read or written from/to USB FIFO. RWADDR[5:0] Reserved Version 1.5 SONiX TECHNOLOGY CO., LTD Page 115...

  • Page 116: Usb Read/Write Data Register (Usb_Rwdata)

    USB FIFO address to be read or written from/to USB FIFO. RWADDR[5:0] Reserved 10.9.19 USB Read/Write Data Register2 (USB_RWDATA2) Address Offset: 0x88 Reset value: 0x0000 0000 Name Description Attribute Reset Data to be read or written from/to USB FIFO. 31:8 RWDATA[31:0] Version 1.5 SONiX TECHNOLOGY CO., LTD Page 116...

  • Page 117: Usb Read/Write Status Register 2(Usb_Rwstatus2)

    When hardware has completed the write action (RWDATA content has been read as the new data, and the new data is written into USB FIFO with address RWADDR.), this bit is automatically cleared as ‘0’ by hardware. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 117...

  • Page 118: Flash

    The FLASH memory may be programmed via the SONiX 32-bit MCU programming interface or by application code for maximum flexibility. SONiX 32-bit MCU provides security options at the disposal of the designer to prevent unauthorized access to information stored in FLASH memory.

  • Page 119: Organization

    To ensure that there is no over-programming, the Flash programming and erase controller blocks are clocked by IHRC. 11.7 EMBEDDED BOOT LOADER The embedded boot loader is used to reprogram the Flash memory using the USB interface. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 119...

  • Page 120: Flash Memory Controller (Fmc)

    1. Mass erase the User ROM first. User shall NOT execute this operation in debug mode, since the SWD communication may fail during the mass erase procedure. 2. Update security level. includes: - New option byte programming includes: - Option byte erase - Mass Erase Version 1.5 SONiX TECHNOLOGY CO., LTD Page 120...

  • Page 121: Program Flash Memory

    HW before reprogramming the read protection option. 11.10 HW CHECKSUM HW checksum is the checksum of User ROM. If the read protection is enabled, the users can still readout the HW checksum through Writer or ISP AP. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 121...

  • Page 122: Fmc Registers

    This bit is set only by SW and reset when the BUSY bit resets. Start Erase/Programming operation. START 1: Triggers an Erase/Programming operation. This bit is set only by SW and resets when the BUSY bit resets. 0: Stop/Finish operation. Reserved Version 1.5 SONiX TECHNOLOGY CO., LTD Page 122...

  • Page 123: Flash Data Register (Flash_Data)

    Choose the Flash address to erase when Page Erase is selected, or to program when Page Program is selected. 11.11.6 Flash Checksum register (FLASH_CHKSUM) Address offset: 0x14 Name Description Attribute Reset 31:16 Reserved 15:0 CHKSUM[15:0] Checksum of User ROM. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 123...

  • Page 124: Serial-Wire Debug (Swd)

    FW any more. SONiX provide Boot loader to check the status of P3.5 (BOOT pin) during boot procedure. If P3.5 is Low during Boot procedure, MCU will execute code in Boot loader instead of User code, so SWD function is not disabled.

  • Page 125: Internal Pull-Up/Down Resitiors On Swd Pins

    To avoid any uncontrolled IO levels, the device embeds internal pull-up and pull-down resistor on the SWD input pins:  SWDIO/JTMS: Internal pull-up  SWCLK/JTCK: Internal pull-down Once a SWD function is disabled by SW, the GPIO controller takes control again. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 125...

  • Page 126: Development Tool

    SN32F260 Series 32-Bit Cortex-M0 Micro-Controller DEVELOPMENT TOOL SONiX provides an Embedded ICE emulator system to offer 32-bit series MCU firmware development. SONiX 32-bit series Embedded ICE Emulator System includes:  SONiX 32-bit MCU Starter-Kit.  SN-LINK-V3.0  USB cable to provide communications between the SN-LINK-V3.0 and PC.

  • Page 127: Sn-Link-V3.0

    13.1 SN-LINK-V3.0 SN-LINK-V3.0 is a high speed emulator for SONiX 32-bit MCU. It debugs and programs based on SWD protocol. In addition to debugger functions, the SN-LINK-V3.0 also may be used as a programmer to load firmware from PC to MCU for engineering production, even mass production.

  • Page 128: Sn32F268 Starter-Kit

    SN32F268 STARTER-KIT SONiX 32-bit MCU Starter-kit is an easy-development platform. It includes real chip and I/O connectors to input signal or drive extra device of user’s application. It is a simple platform to develop application as target board not ready. The starter-kit can be replaced by target board because of integrated SWD debugger circuitry.

  • Page 129: Electrical Characteristic

    GPIO outputs driven LOW and pull-up resistors disabled and VDD=5V. [2] IHRC and ILRC are enabled. [3] LVD and GPIO peripherals are enabled. [4] IHRC is disabled, ILRC is enabled. [5] All oscillators and analog blocks are turned off. Version 1.5 SONiX TECHNOLOGY CO., LTD Page 129...

  • Page 130: Flash Rom Programming Pin

    SN32F260 Series 32-Bit Cortex-M0 Micro-Controller FLASH ROM PROGRAMMING PIN Programming Information of SN32F260 Series Chip Name SN32F268F SN32F267J SN32F265J SN32F2641J SN32F264S/X SN32F263X MP PRO Writer Flash IC / JP3 Pin Assignment Connector Number Name Number Pin Number Number Number Number Pin Number P0.1...

  • Page 131: Package Information

    32-Bit Cortex-M0 Micro-Controller PACKAGE INFORMATION 16.1 LQFP 48 PIN SYMBOLS (mm) 0.05 0.15 1.35 1.45 0.09 0.16 9.00 BSC 7.00 BSC 9.00 BSC 7.00 BSC 0.5 BSC 0.17 0.27 0.45 0.75 1 REF Version 1.5 SONiX TECHNOLOGY CO., LTD Page 131...

  • Page 132: Qfn 46 Pin

    SN32F260 Series 32-Bit Cortex-M0 Micro-Controller 16.2 QFN 46 PIN Version 1.5 SONiX TECHNOLOGY CO., LTD Page 132...

  • Page 133: Sop 28 Pin

    0.305 0.697 0.705 0.713 17.704 17.907 18.110 0.291 0.295 0.299 7.391 7.493 7.595 0.394 0.407 0.419 10.008 10.325 10.643 0.016 0.033 0.050 0.406 0.838 1.270 θ° 0° 4° 8° 0° 4° 8° Version 1.5 SONiX TECHNOLOGY CO., LTD Page 133...

  • Page 134: Ssop 28 Pin

    0.39 0.40 0.41 7.40 7.80 8.20 0.29 0.31 0.32 5.00 5.30 5.60 0.20 0.21 0.22 0.0259BSC 0.65BSC 0.63 0.90 1.03 0.02 0.04 0.04 0.09 0.00 θ° 0° 4° 8° 0° 4° 8° Version 1.5 SONiX TECHNOLOGY CO., LTD Page 134...

  • Page 135: Qfn 28 Pin

    4.00 BSC 0.16 BSC 4.00 BSC 0.016 BSC 0.40 BSC 0.014 0.016 0.018 0.35 0.40 0.45 0.008 0.20 D2 (mm) E2 (mm) PAD SIZE 115x115 MIL 2.50 2.60 2.65 2.50 2.60 2.65 Version 1.5 SONiX TECHNOLOGY CO., LTD Page 135...

  • Page 136: Qfn 33 Pin

    SN32F260 Series 32-Bit Cortex-M0 Micro-Controller 16.6 QFN 33 PIN Version 1.5 SONiX TECHNOLOGY CO., LTD Page 136...

  • Page 137: Ssop 24 Pin

    SN32F260 Series 32-Bit Cortex-M0 Micro-Controller 16.7 SSOP 24 PIN Version 1.5 SONiX TECHNOLOGY CO., LTD Page 137...

  • Page 138: Marking Definition

    SN32F260 Series 32-Bit Cortex-M0 Micro-Controller MARKING DEFINITION 17.1 INTRODUCTION There are many different types in SONiX 32-bit MCU production line. This note lists the marking definitions of all 32-bit MCU for order or obtaining information. 17.2 MARKING INDETIFICATION SYSTEM SN32 X Part No.

  • Page 139: Marking Example

    Green Package SN32F264SG Flash memory -40℃~85℃ Green Package -40℃~85℃ SN32F264XG Flash memory SSOP Green Package -40℃~85℃ SN32F263XG Flash memory SSOP Green Package -40℃~85℃ SN32F268W Flash memory Wafer -40℃~85℃ SN32F268H Flash memory Dice Version 1.5 SONiX TECHNOLOGY CO., LTD Page 139...

  • Page 140: Datecode System

    ..9=09 A=10 B=11 ..1=January Month 2=February ..9=September A=October B=November C=December 03= 2003 Year 04= 2004 05= 2005 06= 2006 ..Version 1.5 SONiX TECHNOLOGY CO., LTD Page 140...
  • Page 141 SONIX product could create a situation where personal injury or death may occur.

This manual is also suitable for:

Sn32f268Sn32f267Sn32f265Sn32f264Sn32f2641Sn32f263

Table of Contents