HP E1328A User Manual page 61

Status Bit Precedence
Note
Note
Appendix B
In addition to bit 0 indicating the DAC ready condition, bit 0 also
determines the validity of bits 6 - 11. When bit 0 is cleared (0), bits 6 - 11
may be invalid. Therefore, when monitoring bits 6 - 11, that bit AND bit 0
must both be true.
PAS: (Passed - bit 2). A zero (0) in this field indicates that the D/A
Converter is either executing, or has failed a self test. A one (1) indicates
that the self test has successfully completed.
READY: (Ready - bit 3). A zero (0) in this field in combination with a one
(1) in the PAS field indicates that the D/A Converter is executing an
extended self test. Note: This bit was formerly called EX* (Extended (not)).
CF*: (Checksum-failure (not) - bit 4). A zero (0) in this field indicates that
the D/A Converter's stored adjustment constants did not have the correct
checksum, and may be incorrect.
If CF* is asserted, it is recommended that each channel be calibrated in both
voltage and current modes before using the D/A Converter in the calibrated
mode.
IE*: (Internal-exception (not) - bit 5). A zero (0) in this field indicates that
the D/A Converter has encountered an error in executing its program. To
clear the error, perform the steps below.
1. Write correct CAL-ON/CAL-OFF commands to each channel.
2. Write correct output data to each channel (ignore the state of the
settle bits).
3. Issue a RESTART command.
4. When IE* is one (1), repeat steps 1 and 2.
5. If this procedure fails, perform a soft reset.
Performing a soft reset (SR) will zero all outputs, cause the D/A Converter to
execute a self-test, and assert the SYSFAIL line. Therefore, it is recommended
that the SFI bit be set before performing a soft reset to avoid halting mainframe
operations.
HP E1328A Register-Based Programming 61