Siemens DQ 4x24VDC/2A HS User Manual page 24

Simatic et 200sp digital output module

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Parameters/address space

4.5 Oversampling

Chronological sequence

The figure below shows the chronological sequence for oversampling. The output data

present in the CPU is output in the data cycle after the next one, distributed across the

sub-cycles which are generated on the actual module.

Sub-cycle

Figure 4-5

Derating

See the information on derating of the module in the section Derating of the

DQ 4x24VDC/2A HS (Page 36).

Output values from bus cycle n

4 bit x 32 (max) each = max. 16 bytes output data per data cycle

Oversampling

Digital output module DQ 4x24VDC/2A HS (6ES7132-6BD20-0DA0)

Manual, 03/2015, A5E34944434-AA

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