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Manuals and User Guides for Freescale Semiconductor MC9S12ZVHL64. We have 1 Freescale Semiconductor MC9S12ZVHL64 manual available for free PDF download: Reference Manual

Freescale Semiconductor MC9S12ZVHL64 Reference Manual

Freescale Semiconductor MC9S12ZVHL64 Reference Manual (874 pages)

MC9S12ZVHY Series; MC9S12ZVHL Series

Brand: Freescale Semiconductor | Category: Microcontrollers | Size: 9 MB

Table of Contents

Device Overview Mc9S12Zvhy/Mc9S12Zvhl Families

3
- Table of Contents
  3
- Introduction
  23
- Features
  24
- Maskset 0N39G and 1N39G Device Compare
  25
- Module Features
  26
- Chapter 1
  
  27
  - Embedded Memory
    27
  - Clocks, Reset & Power Management Unit (CPMU)
    28
  - Main External Oscillator (XOSCLCP)
    29
  - Timer (TIM)
    30
  - Stepper Motor Controller (MC)
    31
  - Inter-IC Bus Module (IIC)
    32
  - Supply Voltage Sensor (BATS)
    33
  - Block Diagram
    34
  - Device Memory Map
    35
  - Part ID Registers Assignments
    38
- Chapter 10
  
  39
  - Detailed Signal Descriptions
    39
  - VSENSE - Voltage Sensor Input
    46
  - Package and Pinouts
    47
    
    Modes of Operation
    58
    
    Debugging Modes
    59
  - Security
    60
    
    Operation of the Secured Microcontroller
    61
    
    Reprogramming the Security Bits
    62
    
    Interrupt Vectors
    63
    
    Effects of Reset
    66
  - COP Configuration
    67
  - The ADC0 VRH/VRL
    68
  - BDC Clock Source Connectivity
    69
  - LCD Clock Source Connectivity
    70
  - Introduction
    71
- Chapter 23
  
  72
  - Features
    72
    
    External Signal Description
    73
    
    Memory Map and Register Definition
    82
- Chapter 2
  
  83
  - Register Map
    83
    
    Register Descriptions
    90
    
    Functional Description
    107
    
    Interrupts
    111
  - Pin Interrupts and Wakeup
    112
  - Initialization and Application Information
    113
  - Introduction
    115
- Chapter 5
  
  116
  - Glossary
    116
    
    Block Diagram
    117
    
    Register Descriptions
    118
    
    Functional Description
    123
  - Illegal Accesses
    125
  - Uncorrectable ECC Faults
    126
  - Introduction
    127
  - Glossary
    128
    
    Modes of Operation
    129
    
    External Signal Description
    130
    
    Register Descriptions
    131
    
    Functional Description
    135
- Chapter 4
  
  136
  - S12Z Exception Requests
    136
  - Priority Decoder
    137
  - Interrupt Vector Table Layout
    138
  - Wake up from Stop or Wait Mode
    139
  - Introduction
    141
- Chapter 22
  
  142
  - Features
    142
    
    Block Diagram
    144
    
    External Signal Description
    145
    
    Register Descriptions
    146
    
    Functional Description
    150
  - Clock Source
    151
Table of Contents

154
- Classification
  155
- Dump_Mem.sz
  158
- Dump_Mem.sz_Ws
  158
- Non-Intrusive no (0X33+4 X Sz)/D/Ss/Rd.sz
  158
- Fill_Mem.sz
  159
- Fill_Mem.sz_Ws
  159
- Non-Intrusive no (0X13+4 X Sz)/Wd.sz/D/Ss
  159
- Go_Until
  161
- Nop
  161
- Read_Rn
  161
- Non-Intrusive no
  162
- Non-Intrusive Yes
  162
- Read_Mem.sz
  162
- Read_Mem.sz_Ws
  162
- Read_Dbgtb
  163
  - BDC Access of Internal Resources
    167
  - BDC Serial Interface
    170
  - Serial Interface Hardware Handshake (ACK Pulse) Protocol
    173
  - Hardware Handshake Abort Procedure
    175
  - Hardware Handshake Disabled (ACK Pulse Disabled)
    176
  - Single Stepping
    177
  - Serial Communication Timeout
    178
  - Introduction
    179
  - Overview
    180
  - Modes of Operation
    181
  - External Signal Description
    182
  - Register Descriptions
    185
- Description
  186
  - Functional Description
    206
- Chapter 6
  
  210
  - Events
    210
    
    State Sequence Control
    212
    
    Trace Buffer Operation
    213
    
    Code Profiling
    222
    
    Breakpoints
    226
    
    Application Information
    227
    
    Breakpoints from Other S12Z Sources
    228
    
    Introduction
    229
    
    Features
    230
    
    Modes of Operation
    232
- Chapter 7
  
  235
  - S12CPMU_UHV_V5 Block Diagram
    235
    
    Signal Description
    237
    
    BCTL — Base Control Pin for External PNP
    238
    
    Memory Map and Registers
    239
    
    Register Descriptions
    241
    
    Functional Description
    279
  - Startup from Reset
    281
  - Stop Mode Using PLLCLK as Source of the Bus Clock
    282
  - External Oscillator
    284
  - System Clock Configurations
    285
  - Resets
    286
  - Description of Reset Operation
    287
  - PLL Clock Monitor Reset
    288
  - Power-On Reset (POR)
    289
  - Interrupts
    290
  - Initialization/Application Information
    292
  - Introduction
    295
    
    S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor
    296
    
    External Signal Description
    299
    
    Register Descriptions
    300
    
    Functional Description
    316
- Chapter 8
  
  318
  - Prescaler
    318
  - Pulse Accumulator
    319
  - Event Counter Mode
    320
  - Channel [7:0] Interrupt (C[7:0]F)
    321
    
    Introduction
    323
    
    Block Diagram
    324
    
    PWM7 - PWM0 — PWM Channel 7 - 0
    325
  - Functional Description
    340
- Chapter 9 PWM Channel Timers
  
  343
  - Resets
    351
  - Interrupts
    352
  - Introduction
    353
  - Key Features
    355
    
    Modes of Operation
    356
    
    Block Diagram
    359
  - Signal Description
    360
10.4 Memory Map and Register Definition

361
- Memory Map and Register Definition
  361
- Address Name Bit
  362
- Radc_En
  364
  - Register Descriptions
    364
- Rcsl_Sel
  367
- Eol_Eie
  374
- Reserved
  375
- Seqad_Ie Conif_Oie
  375
- Cmd_Eif
  376
- Eol_Eif
  376
- Ldok_Eif
  376
- Reserved TRIG_EIF
  376
- Rstar_Eif
  376
- Eol_Ie
  379
- Eol_If
  380
  - Functional Description
    396
  - Digital Sub-Block
    397
  - Resets
    410
  - ADC Error and Conversion Flow Control Issue Interrupt
    411
  - Use Cases and Application Information
    412
  - List Usage — CSL Double Buffer Mode and RVL Double Buffer Mode
    413
  - List Usage — CSL Double Buffer Mode and RVL Double Buffer Mode
    414
  - Conversion Flow Control Application Information
    416
  - Continuous Conversion
    418
  - Triggered Conversion — Single CSL
    419
  - Fully Timing Controlled Conversion
    420
  - Introduction
    421
  - Glossary
    422
  - Features
    423
  - External Signal Description
    424
  - S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor
    425
  - Register Descriptions
    427
  - Programmer's Model of Message Storage
    446
  - Functional Description
    457
  - Identifier Acceptance Filter
    460
  - Modes of Operation
    466
  - Low-Power Options
    468
  - Reset Initialization
    472
  - Initialization/Application Information
    474
  - Introduction
    475
  - Features
    476
  - Modes of Operation
    477
  - External Signal Description
    478
  - Register Descriptions
    479
  - Functional Description
    492
- Chapter 12
  
  493
  - Infrared Interface Submodule
    493
  - Data Format
    494
  - Baud Rate Generation
    495
  - Transmitter
    496
  - Receiver
    501
  - Single-Wire Operation
    509
  - Loop Operation
    510
- Chapter 16
  
  511
  - Modes of Operation
    511
  - Recovery from Wait Mode
    514
  - Introduction
    515
  - Block Diagram
    516
    
    External Signal Description
    517
    
    SS — Slave Select Pin
    518
    
    Register Descriptions
    519
    
    Functional Description
    527
- Chapter 13
  
  528
  - Master Mode
    528
  - Slave Mode
    529
  - Transmission Formats
    530
  - SPI Baud Rate Generation
    535
  - Special Features
    536
  - Error Conditions
    537
  - Low Power Mode Options
    538
  - Introduction
    541
  - Modes of Operation
    543
    
    External Signal Description
    544
    
    Functional Description
    556
- Chapter 14
  
  561
  - Operation in Run Mode
    561
  - Application Information
    562
    
    S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor
    564
    
    Introduction
    569
    
    Features
    570
    
    External Signal Description
    572
    
    Register Descriptions
    574
  - Functional Description
    581
- Chapter 15
  
  583
  - Operation in Wait Mode
    583
  - LCD Waveform Examples
    584
  - LCD Clock Inputs & Reset Behavior
    590
  - Resets
    591
    
    Introduction
    593
    
    Block Diagram
    595
    
    External Signal Description
    596
    
    Register Descriptions
    598
    
    Functional Description
    605
    
    PWM Duty Cycle
    617
    
    Output Switching Delay
    618
    
    Operation in Wait Mode
    619
    
    Initialization/Application Information
    620
    
    Introduction
    621
    
    Block Diagram
    622
    
    External Signal Description
    623
  - Memory Map and Register Definition
    624
  - Functional Description
    631
- Chapter 17
  
  632
  - Return to Zero Modes
    632
  - Operation in Low Power Modes
    636
  - Introduction
    639
    
    Block Diagram
    640
    
    External Signal Description
    641
- Chapter 18
  
  642
  - Ircclk
    642
  - RTC Control Register 1(RTCCTL1)
    643
  - RTC Control Register 2 (RTCCTL2)
    644
  - RTC Control Register 4 (RTCCTL4)
    645
  - RTC Status Register 1 (RTCS1)
    646
  - RTC Compensation Configure Register (RTCCCR)
    647
  - RTC Modulo Register (RTCMOD)
    648
  - RTC Minute Register (RTCMINR)
    649
  - Functional Description
    650
  - RTC Clock Compensation
    651
  - Calendar Register and Bit Write Protection
    652
  - Load Buffer Register
    653
    
    S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor
    654
    
    Introduction
    655
    
    External Signal Description
    656
    
    Memory Map and Register Definition
    657
    
    Functional Description
    668
- Chapter 19
  
  669
  - SSG Tone Generation
    669
  - SSG Start and Stop
    672
  - Register Reload
    673
  - SSG Output Control
    674
    
    Introduction
    675
    
    Register Descriptions
    677
    
    Functional Description
    681
- Chapter 20
  
  682
  - Aligned 2 and 4 Byte Memory Write Access
    682
  - Memory Read Access
    683
  - ECC Algorithm
    684
- Chapter 21 64 KB Flash Module (S12ZFTMRZ64K2KV2)
  
  687
  - Introduction
    688
  - Features
    689
  - External Signal Description
    690
  - Memory Map and Registers
    691
    
    Register Descriptions
    695
    
    Functional Description
    715
    
    Internal NVM Resource
    716
    
    Allowed Simultaneous P-Flash and EEPROM Operations
    721
    
    Flash Command Description
    722
    
    Interrupts
    738
    
    Stop Mode
    739
    
    Unsecuring the MCU in Special Single Chip Mode Using BDM
    740
    
    Introduction
    741
    
    Block Diagram
    742
    
    VSUP — Voltage Supply Pin
    743
    
    Register Descriptions
    744
  - Functional Description
    749
    
    Interrupts
    750
    
    Introduction
    753
    
    Modes of Operation
    754
    
    Block Diagram
    755
    
    S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor
    756
  - Memory Map and Register Definition
    757
    
    Register Descriptions
    758
    
    Functional Description
    765
    
    Modes
    766
    
    Interrupts
    769
    
    Application Information
    772
  - A.1 General
    775
- Appendix A
  
  776
  - A.1.2 Pins
    776
  - A.1.3 Current Injection
    777
  - A.1.4 Absolute Maximum Ratings
    778
  - A.1.6 Operating Conditions
    779
  - A.1.7 Power Dissipation and Thermal Characteristics
    780
  - A.1.8 I/O Characteristics
    783
  - A.1.9 Supply Currents
    785
  - A.1.10 ADC Conversion Result Reference
    787
- Appendix B
  
  789
  - B.1 ADC Operating Characteristics
    789
    
    B.1.2 ADC Accuracy
    791
  - C.1 Reset, Oscillator and PLL
    795
- Appendix D IRC Electrical Specifications
  
  797
- Appendix C Appendix D
  
  798
- Appendix E
  
  799
  - E.1 LCD Driver
    799
  - F.1 MSCAN Electrical Characteristics
    801
- Appendix F
  
  803
- Appendix G
  
  803
  - G.1 NVM Timing Parameters
    803
  - G.2 NVM Reliability Parameters
    804
- Appendix H
  
  807
- Appendix I VREG Electrical Specifications
  
  811
  - VREG Electrical Specifications
    812
  - J.1 OSCLCP Electrical Characteristics
    813
- Appendix J
  
  815
- Appendix K
  
  815
  - K.1 DC Electrical Specifications
    815
- Appendix L
  
  817
  - L.1 Master Mode
    817
  - S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor
    819
- Appendix M
  
  823
  - M.1 Maximum Ratings
    823
  - M.3 Dynamic Electrical Characteristics
    824
- Appendix N Ordering Information
  
  827
- Appendix O
  
  828
  - O.1 144 Lqfp
    829
  - O.2 100 Lqfp
    832
  - P.1 Detailed Register Map
    836
- Appendix P Detailed Register Address Map
  
  837

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