Table of Contents
Advertisement
1.3 Block Diagrams
V
DD
POWER
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
MOTOROLA
6
E
V
XTAL
EXTAL
4XOUT
SS
OSCILLATOR
CLOCK
LOGIC
PULSE
PAI/0C1
ACCUMULATOR
OC2/OC1
OC3/OC1
SYSTEM
OC4/OC1
IC4/OC5/OC1
IC3
IC2
IC1
512 BYTES EEPROM
1024 BYTES STATIC RAM
CPU
CORE
ADDRESS BUS
PORT B
PORT F
Figure 1 MC68HC11F1 Block Diagram
MODA/
IRQ
XIRQ RESET
LIR
MODE
INTERRUPT
LOGIC
CONTROL
COP
CONVERTER
TIMER
PERIODIC INTERRUPT
SELECTS
DATA BUS
PORT C
DDRC
MODB/
V
STBY
V
RH
A/D
V
RL
AN7
PE7
AN6
PE6
AN5
PE5
AN4
PE4
AN3
PE3
AN2
PE2
AN1
PE1
AN0
PE0
PG7
CSPROG
CSGEN
PG6
CSIO1
PG5
CSIO2
PG4
PG3
PG2
PG1
PG0
CHIP
RxD
PD0
SCI
TxD
PD1
MISO
PD2
MOSI
PD3
SCK
PD4
SS
PD5
SPI
MC68HC11F1/FC0
MC68HC11FTS/D
Advertisement
Table of Contents
