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SPR[1:0] — SPI Clock Rate Selects
These two bits select the SPI clock (SCK) rate when the device is configured as a master. When the
device is configured as a slave, the bits have no effect. Refer to Table 23.
Input
SPR[1:0] = 00
Frequency
1 MHz
2 MHz
3 MHz
4 MHz
5 MHz
6 MHz
Any E
The SPRBYP bit in OPT2 on the MC68HC11FC0 allows the SPI baud rate counter
to be bypassed. This permits a maximum master mode baud rate equal to the E-
clock frequency on the MC68HC11FC0. SPRBYP is not present on the
MC68HC11F1.
SPSR — SPI Status Register
Bit 7
SPIF
WCOL
RESET:
0
SPIF — SPI Transfer Complete Flag
SPIF is set when an SPI transfer is complete. It is cleared by reading SPSR with SPIF set, followed by
a read or write of SPDR.
WCOL — Write Collision
WCOL is set when SPDR is written while a transfer is in progress. It is cleared by reading SPSR with
WCOL set, followed by a read or write of SPDR.
0 = No write collision
1 = Write collision
Bit 5 — Not Implemented. Reads always return zero and writes have no effect.
MODF — Mode Fault
A mode fault terminates SPI operation. Set when SS is pulled low while MSTR = 1. MODF is cleared
by reading SPSR read with MODF set, followed by a write to SPCR.
0 = No mode fault
1 = Mode fault
Bits [3:0] — Not Implemented. Reads always return zero and writes have no effect.
SPDR — SPI Data Register
Bit 7
Bit 7
Incoming SPI data is double buffered. Outgoing SPI data is single buffered.
MC68HC11F1/FC0
MC68HC11FTS/D
Table 23 SPI Baud Rates
SPR[1:0] = 01
500 kbps
250 kbps
1 Mbps
500 kbps
1.5 Mbps
750 kbps
2 Mbps
1 Mbps
2.5 Mbps
1.25 Mbps
3 Mbps
1.5 Mbps
E/2
E/4
6
5
4
0
MODF
0
0
0
6
5
4
6
5
4
SPR[1:0] = 10
62.5 kbps
125 kbps
187.5 kbps
250 kbps
312.5 kbps
375 kbps
E/16
NOTE
3
2
0
0
0
0
3
2
3
2
SPR[1:0] = 11
31.25 kbps
62.5 kbps
93.75 kbps
125 kbps
156.25 kbps
187.5 kbps
E/32
$x029
1
Bit 0
0
0
0
0
$x02A
1
Bit 0
1
Bit 0
MOTOROLA
51
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