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A.2.5
MODE 4 – software triggered strobe
After the mode is set, the output will be high. When the count is loaded, the counter
will begin counting. On terminal count, the output will go low for one input clock
period then go high again. If you reload the count register during counting, the new
count will be loaded on the next CLK pulse. The count will be inhibited while the
GATE input is low.
A.2.6
MODE 5 – Hardware triggered strobe
The counter will start counting after the rising edge of the trigger input and will go low
for one clock period when the terminal count is reached. The counter is retriggerable.
A.3
Counter operations
A.3.1
Read/write operation
Before you write the initial count to each counter, you must first specify the read/write
operation type, operating mode and counter type in the control byte and write the
control byte to the control register [BASE + 27(Dec)].
Since the control byte register and all three counter read/write registers have sepa-
rate addresses and each control byte specifies the counter it applies to (by SC1 and
SC0), no instructions on the operating sequence are required. Any programming
sequence following the 8254 convention is acceptable.
There are three types of counter operation: read/load LSB, read /load MSB and read
/load LSB followed by MSB. It is important that you make your read/write operations
in pairs and keep track of the byte order.
A.3.2
Counter read-back command
The 8254 counter read-back command lets you check the count value, programmed
mode and current states of the OUT pin and Null Count flag of the selected coun-
ter(s). You write this command to the control word register. Format is as shown at the
beginning of this section.
The read-back command can latch multiple counter output latches. Simply set the
CNT bit to 0 and select the desired counter(s). This single command is functionally
equivalent to multiple counter latch commands, one for each counter latched.
The read-back command can also latch status information for selected counter(s) by
setting STA bit = 0. The status must be latched to be read; the status of a counter is
accessed by a read from that counter. The counter status format appears at the
beginning of the chapter.
A.3.3
Counter latch operation
Users often want to read the value of a counter without disturbing the count in prog-
ress. You do this by latching the count value for the specific counter then reading the
value.
The 8254 supports the counter latch operation in two ways. The first way is to set bits
RW1 and RW0 to 0. This latches the count of the selected counter in a 16-bit hold
register. The second way is to perform a latch operation under the read-back com-
mand. Set bits SC1 and SC0 to 1 and CNT = 0. The second method has the advan-
tage of operating several counters at the same time. A subsequent read operation on
the selected counter will retrieve the latched value.
23
PCI-1750 User Manual
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