Interrupt Function; Introduction; Irq Level; Interrupt Control Register [Base + 32(Dec)] - Advantech PCI-1750 User Manual

3.4

Interrupt Function

3.4.1

Introduction

Four input channels (IDI 0, IDI 4, IDI 8 and IDI 12) and the output of Timer 1 and
Counter 2 are connected to the interrupt circuitry. The "Interrupt Control Register" of
the PCI-1750 controls how the combination of the six signals generates an interrupt.
Two interrupt request signals, designated "interrupt group 0" and "interrupt group 1",
can be generated at the same time, and then the software can service these two
request signals by ISR. IDI 0, IDI 4 and Timer 1 are connected to interrupt port 0, IDI
8, IDI 12 and Counter 2 are connected to interrupt port 1. The dual interrupt sources
provide the card with more capability and flexibility.
3.4.2

IRQ Level

The IRQ level is set automatically by the PCI plug and play BIOS and is saved in the
PCI controller. There is no need for users to set the IRQ level. Only one IRQ level is
used by this card, although it has two interrupt sources.
3.4.3

Interrupt Control Register [Base + 32(Dec)]

The "Interrupt Control Register" [Base + 32(Dec)] controls the interrupt signal source,
edge and flag. Table 3.1 shows the bit map of the interrupt control register. The regis-
ter is a readable/writable register.When writing to it, it is used as a control register,
and when reading from it, it is use data status register.
Table 3.1: Interrupt control register bit map
Interrupt
Source #
Bit # D7
Abbreviation F1
M00 and M01: "mode bits" of interrupt Group 0
M10 and M11: "mode bits" of interrupt Group 1
E0,E1: triggering edge control bits
F0, F1: flag bits
PCI-1750 User Manual
Interrupt Group 1
D6 D5 D4
E1 M11 M10
Interrupt Group 0
D3 D2
F0 E0
16
D1 D0
M01 M00