Intel S1200SPL Technical Spesification page 135

Intel® Server Board S1200SP Family Technical Product Specification
MSB
LEDs
LED #7
8h
Status ON
1
Results
Ah
Upper nibble bits = 1010b = Ah; Lower nibble bits = 1100b = Ch; the two are concatenated as ACh
The following table provides a list of all POST progress codes.
Diagnostic LED Decoder
1 = LED On, 0 = LED Off
Checkpoint Upper Nibble
MSB
8h 4h
LED # #7 #6
SEC Phase
01h 0 0
02h 0 0
03h 0 0
04h 0 0
05h 0 0
06h 0 0
07h 0 0
08h 0 0
09h 0 0
0Eh 0 0
0Fh 0 0
PEI Phase
10h 0 0
11h 0 0
15h 0 0
19h 0 0
MRC Process Codes – MRC Progress Code Sequence is executed
PEI Phase continued...
31h 0 0
33h 0 0
34h 0 0
4Fh 0 1
DXE Phase
60h 0 1
61h 0 1
62h 0 1
63h 0 1
65h 0 1
Table 61. POST Progress Code LED Example
Upper Nibble AMBER LEDs
LED #6 LED #5
4h 2h
OFF ON
0 1
Table 62. POST Progress Codes
Lower Nibble
2h 1h 8h 4h 2h
#5 #4 #3 #2 #1
0 0 0 0 0
0 0 0 0 1
0 0 0 0 1
0 0 0 1 0
0 0 0 1 0
0 0 0 1 1
0 0 0 1 1
0 0 1 0 0
0 0 1 0 0
0 0 1 1 1
0 0 1 1 1
0 1 0 0 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
1 1 0 0 0
1 1 0 0 1
1 1 0 1 0
0 0 1 1 1
1 0 0 0 0
1 0 0 0 0
1 0 0 0 1
1 0 0 0 1
1 0 0 1 0
LED #4 LED #3
1h 8h
OFF ON
0 1
Ch
LSB
1h
#0
1 First POST code after CPU reset
0 Microcode load begin
1 CRAM initialization begin
0 Pei Cache When Disabled
1 SEC Core At Power On Begin.
0 Early CPU initialization during Sec Phase.
1 Early SB initialization during Sec Phase.
0 Early NB initialization during Sec Phase.
1 End Of Sec Phase.
0 Microcode Not Found.
1 Microcode Not Loaded.
0 PEI Core
1 CPU PEIM
1 NB PEIM
1 SB PEIM
1 Memory Installed
1 CPU PEIM (Cache Init)
0 CPU PEIM (Cpu Init)
1 Dxe IPL started
0 DXE Core started
1 DXE NVRAM Init
0 SB RUN Init
1 DXE CPU Init
1 DXE CPU BSP Select
Lower Nibble GREEN LEDs
LED #2 LED #1
4h 2h
ON OFF
1 0
Description
LSB
LED #0
1h
OFF
0
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