Winmate IK70 User Manual page 71

BIOS Setting Description
Enable Root Port Configure Root
Port
parameters
Max Link Speed Select Max Link
Speed
PEG0 Slot Power PEG0 Slot
Limit Value Power Limit
Value
PEG0 Slot Power Select PEG0
Limit Scale Slot Power
Limit Scale
Program PCIe Program PCIe
ASPM after ASPM after
OpROM OpROM
Program Static Program Static
Phase1 Eq Phase1 Eq
Always Attemp Always Attemp
SW EQ SW EQ
Number of Select number
Presents to test of Presents to
test
Allow PERST # Allow PERST #
GPIO Usage GPIO Usage
SW EQ Enable Select Jitter,
VOC VOC test mode
Generate BDAT Generate BDAT
PEG Margin Data PEG Margin
Data
PCIe Rx CEM PCIe Rx CEM
Setting Option
Enabled
Disabled Auto
Auto
Gen1
Gen2
Gen3
75
1.0x
0.1x
0.01x
0.001x
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
7,3,5,8
0-9
Auto
Disabled
Enabled
-Jitter Only Test
Mode
-Jitter & VOC Test
Mode
-Auto
-Disabled
-Generate Port Gitter
Data
Disabled
Chapter 4: Insyde H20 BIOS Setup
Effect
Enable or disable Root Port
Configure PEG 0:1:0 Max Speed
PEG0 Slot Power Limit Value
Select the scale used for Slot Power
Limit Value
PCIe ASPM will be programmed before
OpROM
PCIe ASPM will be programmed after
OpROM
Program Phase1 Presents/ CTLEp
Always Attemp SW EQ, even it has
been done once
Choose between 7,3,5,8 and 0-9. Auto
= current default (7,3,5,8 for SKL). Do
not change the default unless
debugging.
Enable/ Disable GPIO-based resets to
PEG endpoint(s) during margin search,
if needed
Select Jitter & VOC test mode (default)
or Jitter only test mode. Auto will current
default (Enabled)
Enable to generate BDAT PCIe margin
tables
Enable/ Disable PEG Rx CEM
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