External Memory Interface - Analog Devices ADuC7026 Reference Manual

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Application notes (16 pages)

EXTERNAL MEMORY INTERFACE

A footprint for a 32 kB  16 SRAM is provided on board

as well as a footprint for a 16 -bit D-latch since address

and data are multiplexed on the external bus.

The memory footprint is for a CY7C1020CV33 and the

latch footprint is for a 74LVT16373AGG.

Note that you can use different versions of the

CY7C1020CV33 memory, with different access times.

Wait states can be added in the XMxPAR register to

allow interfacing a slower memory if required.

Connections

Controls: RS, WS, and AE are the minimum control

signals of any memory interface.

MSO, memory select is connected to CE to

enable the memory only when necessary.

BHE and BLE allow the user to select the high

or low byte of the 16 -bit memory.

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Figure 2. External Memory Connections

Data:

16 bits of data AD[15 - 0] are directly con-

nected from the ADuC7026 to the memory.

Addresses:

To address 32 kB, only a 14-bit address is

required.

There are two ways of addressing a 16 -bit

memory:

1. Connecting AD[14-0] to A[14-0]. To enable

it requires dynamic addressing (set Bit 11

in XMxPAR) to address in 16 - bit mode

instead of 8-bit mode.

2. Connecting AD[15-1] of the ADuC702x to

A[14-0] of the memory, without using

dynamic addressing.

On the evaluation board, AD[14-0] are

connected. In software, dynamic addressing

must be enabled.

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External Memory Interface - Analog Devices ADuC7026 Reference Manual

EXTERNAL MEMORY INTERFACE

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