Features Of The Atmel Atmega32Hvb; Coulomb Counter - Atmel ATmega32HVB User Manual

5.

Features of the Atmel ATmega32HVB

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Since the Atmel ATmega32HVB is a part of the Atmel AVR
several special features such as coulomb counting and the control of the two charge/discharge MOSFETs.
5.1

Coulomb Counter

The coulomb counter ADC runs on a different clock than the CPU. This clock is slower and therefore several things have to
be kept in mind before using it. Writing several registers in sequence takes a long time depending on the delays between
each write cycle. A possible solution is given in the supplied software example:
C Code Example
void CCinit(){
CADRCC = RCC_CADRCC;
while(CADCSRA & (1 << CADUB));
CADRDC = RDC_CADRDC;
while(CADCSRA & (1 << CADUB));
SETBIT(CADCSRB,1<<CADRCIE);
while(CADCSRA & (1 << CADUB));
SETBIT(CADCSRC,RCC_DIVIDEDSZ<<CADVSE);
while(CADCSRA & (1 << CADUB));
SETBIT(CADCSRA,((1<<CADEN)|(1<<CADSE)|(RCC_CONVERSIONPERIOD<<1)));
while(CADCSRA & (1 << CADUB));
}
The Update Busy (CADUB) bit in CADSRA is cleared and written by hardware.
5.2 Charging/Discharging FETs
The two FETs are controlled by an N-channel FET driver. The pins (OC and OD) are designed for outputting a high voltage
of approx. 13V. The status of the pins is controlled by software via the FCSR - FET control and status register.
C Code Example
void Configure_Fet(unsigned char Fet){
if(Fet&0x01)
else
if(Fet&0x02)
else
}
The example above implements an easy method to enable or disable the two FETs independently of each other. For more
information, see the Atmel ATmega32HVB datasheet page 148ff.
SETBIT(FCSR, (1<<DFE));
CLEARBIT(FCSR,(1<<DFE));
SETBIT(FCSR,(1<<CFE));
CLEARBIT(FCSR,(1<<CFE));
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family which is dedicated to battery management there are
// Charge Threshold
// Discharge Threshold
// Interrupt Enable
// Voltage Scaling
// ADC Enable, RCC Mode, Sampling
// Interval
ATA6870-DK10 [APPLICATION NOTE] 9
9228C–AUTO–02/15