Counter Reset Conditions - Omron SYSMAC C200H-CT001-V1 Operation Manual

Counter Reset Conditions

3-3 Counter Reset Conditions
Inputs used
Input Z
Control input IN1
Internal reset bit
Input Z
Control input IN1
Input Z
Internal reset bit
Control input IN1
Internal reset bit
Input Z
Control input IN1
Internal reset bit
Counter reset conditions vary according to the combination of inputs used and
pin settings on the back panel DIP switch. The DIP switch settings required for
the input combinations shown in the following table and the operating modes
that can be used with each are shown on the next page. (The numbers 1 through
17 above the input patterns correspond to the settings.) Resetting is not possible
in the gate, latch, and sampling operating modes. All inputs for each pattern
must be in the status shown for setting to be effective. The minimum input pulse
width for the input Z is 0.1 ms;that for the control input IN1, 1 ms.
In the following table, input Z is indicated by Z; control input IN1, by IN1, and the
internal reset bit, by IRB. The point at which the reset actually takes place is indi-
cated by the arrow at the bottom of each pattern. The DIP switch settings for
each pattern are described on the following page.
1
Z
Z
IN1
IN1
IRB IRB
5
Z
Z
IN1
IN1
9
Z Z
IRB
IRB
11
IN1 IN1
IRB
IRB
13
Z Z
15
IN1 IN1
17
IRB
Reset conditions and timings
2 3
Z
IN1
IRB
6 7
Z
IN1
10
12
14
16
Section 3-3
4
Z
IN1
IRB
8
Z
IN1
29