Freescale Semiconductor MC68332 Manuals

Manuals and User Guides for Freescale Semiconductor MC68332. We have 1 Freescale Semiconductor MC68332 manual available for free PDF download: User Manual

Freescale Semiconductor MC68332 User Manual

Freescale Semiconductor MC68332 User Manual (266 pages)

M68300 series

Brand: Freescale Semiconductor | Category: Microcontrollers | Size: 1 MB

Table of Contents

Table of Contents
4
Section 1 Introduction

18
Section 2Nomenclature

20
- Symbols and Operators
  20
- CPU32 Registers
  21
- Pin and Signal Mnemonics
  22
- Register Mnemonics
  23
- Conventions
  24
Section 3Overview

26
- MC68332 Features
  26
- System Integration Module (SIM)
  26
- Central Processing Unit (CPU)
  26
- Time Processor Unit (TPU)
  26
- Queued Serial Module (QSM)
  27
- Static RAM Module with TPU Emulation Capability (TPURAM)
  27
- System Block Diagram and Pin Assignment Diagrams
  27
- Pin Descriptions
  30
- Signal Descriptions
  32
- Intermodule Bus
  34
- System Memory Map
  34
- Internal Register Map
  35
- Address Space Maps
  35
- System Reset
  40
- SIM Reset Mode Selection
  40
- MCU Module Pin Function During Reset
  41
Section 4 System Integration Module

42
- General
  42
- System Configuration and Protection
  43
- Module Mapping
  44
- Interrupt Arbitration
  44
- Show Internal Cycles
  45
- Factory Test Mode
  45
- Register Access
  45
- Reset Status
  45
- Bus Monitor
  46
- Halt Monitor
  46
- Spurious Interrupt Monitor
  46
- Mc68332 User's Manual
  46
- Software Watchdog
  46
- Periodic Interrupt Timer
  48
- Low-Power Stop Operation
  49
- Freeze Operation
  50
- System Clock
  50
- Clock Sources
  51
- Clock Synthesizer Operation
  51
- External Bus Clock
  56
- Low-Power Operation
  56
- Loss of Reference Signal
  57
- External Bus Interface
  58
- Bus Signals
  59
- Address Bus
  59
- Address Strobe
  59
- Data Bus
  59
- Data Strobe
  59
- Read/Write Signal
  59
- Size Signals
  60
- Function Codes
  60
- Data and Size Acknowledge Signals
  60
- Bus Error Signal
  61
- Halt Signal
  61
- Autovector Signal
  61
- Dynamic Bus Sizing
  61
- Operand Alignment
  62
- Misaligned Operands
  63
- Operand Transfer Cases
  63
- Bus Operation
  63
- Synchronization to CLKOUT
  64
- Regular Bus Cycles
  64
- Read Cycle
  65
- Write Cycle
  66
- Fast Termination Cycles
  67
- CPU Space Cycles
  68
- Breakpoint Acknowledge Cycle
  69
- LPSTOP Broadcast Cycle
  72
- Bus Exception Control Cycles
  72
- Bus Errors
  74
- Double Bus Faults
  74
- Retry Operation
  75
- Halt Operation
  75
- External Bus Arbitration
  76
- Slave (Factory Test) Mode Arbitration
  77
- Show Cycles
  77
- Reset
  78
- Reset Exception Processing
  78
- Reset Control Logic
  79
- Reset Mode Selection
  79
- Data Bus Mode Selection
  80
- Clock Mode Selection
  82
- Breakpoint Mode Selection
  82
- MCU Module Pin Function During Reset
  82
- Pin State During Reset
  83
- Reset States of SIM Pins
  83
- Reset States of Pins Assigned to Other MCU Modules
  84
- Reset Timing
  84
- Power-On Reset
  85
- Reset Processing Summary
  86
- Reset Status Register
  87
- Interrupts
  87
- Interrupt Exception Processing
  87
- Interrupt Priority and Recognition
  87
- Interrupt Acknowledge and Arbitration
  88
- Interrupt Processing Summary
  89
- Interrupt Acknowledge Bus Cycles
  90
- Chip Selects
  90
- Chip-Select Registers
  92
- Chip-Select Pin Assignment Registers
  93
- Chip-Select Base Address Registers
  94
- Chip-Select Option Registers
  94
- PORTC Data Register
  96
- Chip-Select Operation
  96
- Using Chip-Select Signals for Interrupt Acknowledge
  96
- Chip-Select Reset Operation
  97
- Parallel Input/Output Ports
  99
- Pin Assignment Registers
  99
- Data Direction Registers
  99
- Data Registers
  99
- Factory Test
  99
Section 5 Central Processing Unit

100
- General
  100
- CPU32 Registers
  101
- Data Registers
  102
- Address Registers
  104
- Program Counter
  104
- Control Registers
  104
- Status Register
  104
- Alternate Function Code Registers
  105
- Vector Base Register (VBR)
  105
- Memory Organization
  105
- Virtual Memory
  107
- Addressing Modes
  107
- Processing States
  107
- Privilege Levels
  108
- Instructions
  108
- M68000 Family Compatibility
  111
- Special Control Instructions
  112
- Low Power Stop (LPSTOP)
  112
- Exception Processing
  112
- Exception Vectors
  112
- Types of Exceptions
  113
- Exception Processing Sequence
  114
- Development Support
  114
- M68000 Family Development Support
  114
- Background Debugging Mode
  114
- Enabling BDM
  116
- BDM Sources
  116
- Entering BDM
  117
- BDM Commands
  118
- Background Mode Registers
  119
- Returning from BDM
  119
- Serial Interface
  119
- Recommended BDM Connection
  121
- Deterministic Opcode Tracking
  121
- On-Chip Breakpoint Hardware
  122
- Loop Mode Instruction Execution
  122
Section 6Queued Serial Module

124
- General
  124
- QSM Registers and Address Map
  125
- QSM Global Registers
  125
- Low-Power Stop Operation
  125
- Freeze Operation
  126
- QSM Interrupts
  126
- QSM Pin Control Registers
  126
- Queued Serial Peripheral Interface
  127
- QSPI Registers
  129
- Control Registers
  130
- Status Register
  130
- Qspi Ram
  130
- Receive RAM
  130
- Transmit RAM
  131
- Command RAM
  131
- QSPI Pins
  131
- QSPI Operation
  132
- QSPI Operating Modes
  133
- Master Mode
  140
- Master Wraparound Mode
  143
- Slave Mode
  143
- Slave Wraparound Mode
  145
- Peripheral Chip Selects
  145
- Serial Communication Interface
  145
- SCI Registers
  145
- Control Registers
  145
- Status Register
  148
- Data Register
  148
- SCI Pins
  148
- SCI Operation
  148
- Definition of Terms
  148
- Serial Formats
  149
- Baud Clock
  149
- Parity Checking
  150
- Transmitter Operation
  150
- Receiver Operation
  151
- Idle-Line Detection
  152
- Receiver Wakeup
  153
- Internal Loop
  153
- QSM Initialization
  154
Section 7Time Processor Unit

156
- General
  156
- TPU Components
  157
- Time Bases
  157
- Timer Channels
  157
- Scheduler
  157
- Microengine
  157
- Host Interface
  157
- Parameter RAM
  158
- TPU Operation
  158
- Event Timing
  158
- Channel Orthogonality
  159
- Interchannel Communication
  159
- Programmable Channel Service Priority
  159
- Coherency
  159
- Emulation Support
  159
- TPU Interrupts
  160
- Standard and Enhanced Standard Time Functions
  161
- Discrete Input/Output (DIO)
  161
- Input Capture/Input Transition Counter (ITC)
  161
- Output Compare (OC)
  161
- Pulse-Width Modulation (PWM)
  162
- Synchronized Pulse-Width Modulation (SPWM)
  162
- Period Measurement with Additional Transition Detect (PMA)
  162
- Period Measurement with Missing Transition Detect (PMM)
  162
- Position-Synchronized Pulse Generator (PSP)
  162
- Stepper Motor (SM)
  163
- Period/Pulse-Width Accumulator (PPWA)
  163
- Quadrature Decode (QDEC)
  164
- Motion Control Time Functions
  164
- New Input Capture/Transition Counter (NITC)
  164
- Queued Output Match (QOM)
  165
- Programmable Time Accumulator (PTA)
  165
- Multichannel Pulse-Width Modulation (MCPWM)
  165
- Fast Quadrature Decode (FQD)
  165
- Universal Asynchronous Receiver/Transmitter (UART)
  166
- Brushless Motor Commutation (COMM)
  166
- Frequency Measurement (FQM)
  166
- Hall Effect Decode (HALLD)
  166
- Host Interface Registers
  166
- System Configuration Registers
  166
- Emulation Control
  168
- Low-Power Stop Control
  168
- Channel Control Registers
  169
- Channel Interrupt Enable and Status Registers
  169
- Channel Function Select Registers
  169
- Host Sequence Registers
  169
- Host Service Registers
  169
- Channel Priority Registers
  169
- Development Support and Test Registers
  170
- Section 8Standby Ram with Tpu Emulation
  
  172
  - General
    172
  - TPURAM Array Address Mapping
    172
  - TPURAM Register Block
    172
  - Normal Operation
    173
  - Standby Operation
    173
  - TPURAM Privilege Level
    173
  - Low-Power Stop Operation
    174
  - Reset
    174
  - TPU Microcode Emulation
    174
- Appendix A Electrical Characteristics
  
  176
Appendix B Mechanical Data and Ordering Information

206
- Appendix Cdevelopment Support
  
  214
  - M68MMDS1632 Modular Development System
    214
  - M68MEVB1632 Modular Evaluation Board
    215
- Appendix D Register Summary
  
  216
  - Central Processing Unit
    216
    
    D.1.1 CPU32 Register Model
    217
    
    D.1.2 SR — Status Register
    218
    
    D.3 Standby RAM Module with TPU Emulation
    231
    
    D.4 Queued Serial Module
    233
    
    D.4.3 QILR — QSM Interrupt Level Register
    234
    
    D.4.9 PQSPAR — PORT QS Pin Assignment Register
    238
    
    D.5.21 TPU Parameter RAM
    252

Advertisement

Advertisement

Related Products

Freescale Semiconductor Categories

Motherboard Computer Hardware Microcontrollers Control Unit Controller

More Freescale Semiconductor Manuals