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COSMAC Microprocessor
49
be stored in memory locations Ql-Q4. The second group of four input bytes represent the desired time
intervals between output states and will be stored in memory locations Tl-T4.
When eight input bytes have been stored, LC will be equal to zero in step 7. In this case, steps 8·9·10 will
be performed next. QP is set to address the Q1 memory byte again. TP is set to address the T1 byte. LC is
set equal to 4 and step 11 is performed to place the Q1 memory byte into the output register. QP is incre·
mented by 1 so that the Q2 byte will be placed in the output register the next time step 11 is performed.
Step 12 sets TC equal to the value of the Tl byte. TP is incremented by 1 so that TC will be set equal to
the value of the T2 byte the next time step 12 is performed.
Step 13 and 14 continually decrement TC until it reaches a value of zero. The time required for TC to
reach zero determines the time interval between the current output state and the next output state. This
time is a function of the clock frequency, the number of instructions in the loop comprising steps 13-14,
and the original value placed in TC.
At the end of the TC counting time, LC is decremented by 1. If LC does not equal zero, the step 11-17
loop is repeated. This loop causes the Q1-Q2-Q3-Q4 output sequence to occur at the specified T1-t2-
T3-T4 time intervals. When LC equals zero at step 17, steps 8, 9, and 10 are performed again to repeat the
Q1-Q2-Q3-Q4 sequence. This four·state output sequence is repeated until the system is stopped. After
applying a clear signal, a new set of state and time bytes can be entered to modify the output sequence.
STEP
I
STEP
2-3
STEP
4-5
STEP
6
STEP
7
STEP
START
8-9-10
L -_ _
~
_ _ _
--l
STEP
II
STEP
12
STEP
13
STEP
14
STEP
15
STEP
L -_ _ _
,.-=-_--l
16-17
92CS- 26482
Fig.
55 -
Sample program flow chart.
Fig. 56 shows the actual instruction bytes in memory required for the program. A low on the
CLEAR
line sets P equal to 0 and
R(O)
equal to 0000. When execution is started, the instruction in memory location
0001 will be fetched and executed as described in the section on Memory and Control Interface. The in-
structions required for each flow-chart step are shown.
Note that in step 12 the time-control byte is placed in the high-order half of R (4) or TC. As a result, the
loop comprising steps 13 and 14 will be executed 256 times to decrement the T byte value by 1. Steps 13
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