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10 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ User Manual for the
an input/output instruction, or none of thp.se. The timing signals are used by the memory and I/O systems to
signal a new processor state code, to latch memory address bits, to take memory data from the bus, and to
set and reset I/O controller flip-flops.
Bytes are transmitted to and from memory by means of the common data bus. COSMAC provides two
lines to control memory read/write cycles. During a memory write cycle, the byte to be written appears on
the data bus and a memory write pulse is generated by COSMAC at the appropriate time. A memory read
level is generated which is used by the system to gate the memory output byte onto the common data bus.
COSMAC provides eight memory address lines. These eight lines supply 16-bit memory addresses in the
form of two successive 8-bit bytes. The more significant (high-order) address byte appears on the eight
address lines first, followed by the less significant (low-order) address byte. The number of high-order bits
required to select a unique memory byte location depends on the size of the memory. For example, a
4096-byte memory would require a 12-bit address. This 12-bit address is obtained by combining 4 bits
from the high-order address byte with the 8 bits from the low-order address byte. One of the two COSMAC
timing pulses strobes the required high-order bits into an address latch (register) when they appear on the
eight address lines. An internal COSMAC register holds the eight low-order address bits on the address lines
for the remainder of the memory cycle. No external latch circuits are required for the low -order address byte.
Three additional lines complete the COSMAC microprocessor system interface. A single-phase clock
input determines operating speed. The external clock may be stopped and started to synchronize COSMAC
operation with system circuits if desired. A single clear input initializes internal COSMAC circuitry in one
step. The load signal line holds the COSMAC microprocessor in the program load mode. The use of this
mode is discussed in the section on Memory and Control Interface.
COSMAC Architecture and Notation
Fig. 2 illustrates the internal structure of the COSMAC microprocessor. This simple, unique architecture
results in a number of system advantages. The COSMAC architecture is based on a register array comprising
sixteen general-purpose 16-bit scratchpad registers. Each scratchpad register, R, is designated by a 4-bit
binary code. Hexadecimal (hex) notation will be used here to refer to 4-bit binary codes. The 16 hexa-
decimal digits (0,1,2, ... E,F) and their binary equivalents (0000,0001,0010, ... ,1110,1111) are listed in
Appendix A.
Using hex notation, R (3) refers to the 16-bit scratch pad register designated or selected by the binary code
0011. R (3).0 refers to the low-order (less significant) eight bits or byte of R (3).
R (3).1 refers to the high-
order (more significant) byte of R(3).
Three 4-bit registers labeled N, P, and X hold 4-bit binary codes (hex digits) that are used to select
individual 16-bit scratch pad registers. The 16 bits contained in a selected scratch pad can be copied into the
16-bit A register. The two A-register bytes are sequentially placed on the eight external memory address
lines for memory read/write operations. Either of the two A-register bytes (A.O/ A.1) can also be gated to
the 8-bit data bus for subsequent transfer to the D register. The 16-bit val ue in the A register can also be
incremented or decremented by 1 and returned to the selected scratch pad register to permit a scratch pad
register to be used as a counter.
The notation R(X), R(N), or R(P) is used to refer to a scratchpad register selected by the 4-bit code in X,
N, or P, respectively. Fig. 3 illustrates the transfer of a scratch pad register byte, designated by N, to D. The
left half of Fig. 3 illustrates the initial contents of various registers (hex notation). The operation performed
can be written as
R(N)_O
-7
D
This expression indicated that the low-order 8 bits contained in the scratch pad register designated by the
hex digit in N are to be placed into the 8-bit D register. The designated scratch pad register is left unchanged.
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