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COSMAC Microprocessor _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 25
the COSMAC state code lines to indicate I/O (1=6). The most significant bit of N is "0", indicating "OUT-
PUT". The I/O system recognizes these conditions, and reads the output byte from the bus. The 3 less
significant bits of N specify which of the 8 output instructions is being executed. R (X) is incremented by ,
so that successively executed output instructions can transfer bytes from successive memory locations.
If X is set to the same value as P, then thf! byte immediately following the output instruction is read out
as immediate data.
N=8-F
INPUT
BUS
-+
M(R(X))
IINP
I
When 1=6 and N=8,9,A,B,C,D,E, or F, an input byte replaces the memory byte addressed by R(X). R(X) is
not modified. The four bits of N are simultaneously sent from COSMAC to the I/O system, and the I/O
state code (1=6) is provided. The most significant bit of N is '" ", indicating "INPUT". The I/O circuits
should gate an input byte onto the data bus during the execute cycle.- The 3 least significant bits of N
specify which of the 8 possible input instructions is being executed. R(X) is not modified.
r-
A
A
A
00
34
I
N
A
cb
p
0
l-
x
2
ADDREoSS
M
I
6
00
31
12
RIOI
03
36
00
32
34
Rill
00
71
IALul-
I
A
00
34J
N
A
cb
p
0
l-
x
2
ADDRESS
M
I
6
00
31
12
RIOI
03
36
00
32
34
Rill
00
71
IALU
I-
I
•
00
33
56
RI21
00
34
I-
DF
=-
00
33
56
RI21
00
34
I-
DF
=-
00
34
78
RI31
-
-
I
D
I- I
00
34
27
RI31
-
-
I
D
I- I
_ _ _ _ _ _
~2~7
_ _ _ _ _ _ _ _ _ _ _ _ _
~~27
f
27
Fig. 31 - Example
of
instruction 6N (N=8-FJ -INPUT.
Branching
The current program counter, R(P), normally steps sequentially through a list of instructions, skipping
over immediate data bytes. When 1=3, a branch instruction is executed. The N code specifies which
condition is tested. If the test is satisfied, a branch is effected by changing R(P).
When a branch condition is satisfied, the byte immediately following the branch instruction replaces the
low-order byte of R(P). The next instruction byte will be fetched from the memory location specified by
the byte following the branch instruction. If the test condition is not satisfied, then execution continues
with the instruction following the immediate byte. This ability to branch to a new instruction sequence
(or back to the beginning of the same sequence to form a loop) is fundamental to stored-program computer
usefulness.
30
UNCONDITIONAL BRANCH
M(R(P))
-+
R(P).O
When 1=3 and N=O, an unconditional branch operation is performed. The byte immediately following the
"30" replaces R (P) .0.
-
A
01
23
N
0
cb
-
P
1
2
X
ADDRESS
M
I
3
01
21
F6
RIO)
-
-
01
22
30
Rill
01
23
-
IALul-
I
A
-01
23
N
0
c6
I-
p
1
X
2
ADDRESS
M
I
3
01
21
F6
RIOI
-
-
01
22
30
Rill
01
82
I-
IALU
I-
I
•
01
23
82
RI21
00
37
DF
=-
01
23
82
R(21
00
37
DF
=-
01
24
2A
RI31
-
-
I
D
I- I
01
24
2A
RI31
-
-
I
D
I- I
~
82
f
Fig. 32 - Example
of
instruction 30 - UNCONDITIONAL BRANCH.
27
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