Advertisement
COSMAC Microprocessor _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 13
The execution of each instruction requires two machine cycles. The first cycle fetches or reads the ap-
propriate instruction byte from memory and stores the two hex instruction digits in registers I and N. The
values in I and N specify the operation to be performed during the second machine cycle. I specifies the in-
struction type. Depending upon the instruction, N either designates a scratch pad register, as illustrated in
Fig. 3, or acts as a special code, as described in more detail below.
Instructions are normally executed in sequence. A program counter is used to address successively the
memory bytes representing instructions. In the COSMAC microprocessor, anyone of the 16-bit scratchpad
registers can be used as a program counter. The value of the hex digit contained in register P determines
which scratch pad register is currently being used, as the program counter. The operations performed by the
instruction fetch cycle are
M{R{P))
-+
I,N;R{P)+l
Fig. 6 illustrates a typical instruction fetch cycle. Register P has been previously set to 1, designating
R (1) as the current program counter. During the instruction fetch cycle, the "0298" contained in R (P) is
placed in A and used to address the memory. The F4 instruction byte at M (0298) is read onto the bus and
then gated into I and N. The value in A is incremented by 1 and replaces the original value in R{P). The
next machine cycle will perform the operation specified by the values in I and N. Following the execute
cycle, another instruction fetch cycle will occur. R{P) designates the next instruction byte in sequence (56).
Alternately repeating instruction fetch execute cycles in this manner causes sequences of instructions that
are stored in memory to be executed.
•
A
02
98
I
N
4
--
cb
I-
p
1
X
7
ADDRESS
M
~
I
F
02
97
46
R(O)
-
-
02
98
F4
r--
R(l)
02
99
-
~
02
99
56
R(2)
-
-
DF =-
02
9A
17
R(3)
-
-
D
-
A
02
98
N
6
cfu
-
P
1
X
7
ADDRESS
M
I
4
02
97
46
R(O)
-
-
02
98
F4
R(l)
02
98
-
IALul-
I
02
99
56
R(2)
-
-
DF=-
02
9A
17
R(3)
-
-
I
D
I-
I
~
F4
Fig.
6 -
Typical instruction fetch cycle.
The COSMAC machine cycle during which an instruction byte is fetched from memory is called state
0
(SO). The cycle during which the fetched instruction is executed is called state 1 (S1). During execution of
a program, COSMAC alternates between SO and S1, as shown below:
... I
SO
I
S1
I
SO
I
Sl
I
SO
I
S1
I ...
Each machine cycle is internally divided into eight equal time intervals, as illustrated in Appendix D
under general timing. Each time interval is equivalent to one external clock cycle (T). The rate at which
machine cycles occur is, therefore, one-eight of the clock frequency. The instruction time is 16T or two
machine cycles. All instructions require the same fetch/execute time.
Advertisement
