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COSMAC Microprocessor
43
DMA-IN. Fig. 49 illustrates the manner in which a DMA input mode might be implemented. TPA is used
to sample the state code to avoid the state transition times (after TPB but before TPA). The input device may
be the same devices discussed in conjunction with Fig. 48. In the DMA case, however, each ENTER pulse
will put a low on the DMA-IN line instead of on a flag line.
4069
eOSMAe
~D~M~A~-~IN~
______________
~Q
Fig.
49 -
DMA input logic.
(ON=H)
INPUT
BYTE
2-4066
JrlL
ENTER PULSE
Vee
92CS - 26480
A low DMA-IN line will automatically modify the normal fetch-execute sequences. If the DMA-IN
line goes low during an instruction fetch cycle (SO)' then the normally following execute cycle (S1) will
still be performed. Following this execute cycle (S1), a special DMA cycle (S2) will be performed. If the
DMA-I N line goes low during an instruction execute cycle (S1), then the DMA cycle (S2) will immediately
follow. If the DMA-I N line is reset to its high state during the DMA
~ycle
(S2) then the deferred next
instruction fetch cycle (SO) will be performed following the S2 cycle, as shown below:
DMA-IN
CYCLES/ST ATES
If the DMA-IN line remains low, S2 cycles will be performed until the DMA-IN line goes high, as shown
below. The DMA mode permits a maximum I/O byte transfer rate of one byte per machine cycle.
DMA-IN
CYC LES/ST ATES
SO
I
S1
SO
S1
S2
S2
S2
I
SO
I
S 1
I
An S2 cycle is indicated by a high SCO line and a low SC1 line. This condition is used to place a DMA
input byte onto the bus, as shown in Fig. 49. The S2 cycle stores the input byte in memory at the location
addressed by R(O). R(O) is then incremented by 1 so that subsequent S2 cycles will store input bytes in
sequential memory locations. S2 cycles do not alter the sequence of program execution. The program will,
however, be slowed down by the S2 cycles that are "stolen". The concurrent program must, of course,
properly use R(O) and memory areas in which input bytes are being stored. It may examine R(O) and the
memory area involved to observe the course of the data transfer. The program must also set R(O) to the ad-
dress of the desired first input byte location in memory before permitting a DMA input operation.
Program Load Facility. The DMA-I N feature, in conjunction with the LOAD and CLEAR signals,
provides a built-in program load mechanism. A low on the CLEAR line resets R (0) to
0000.
If the LOAD
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