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COSMAC Microprocessor _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
35
time of 1 microsecond. The time required by the ALU and internal gating is specified in COSMAC data
sheets.
If a memory does not have a 3-state high-impedance output, M READ is useful for driving memory-bus
separator gates, otherwise it is used to control 3-state outputs from the addressed memory. A low on
MREAD indicates a read cycle; the low MREAD line enables the memory-output-bus gates during the read
cycle (see Appendix 0, COSMAC Timing).
For various memory systems, MREAD signal and the MWR pulse polarity and width may require modi-
fication by external circuitry. Segments of ROM can be attached in the same manner, omitting the write
controls. Dynamic RAM's can be used with appropriate refresh circuits. Since COSMAC circuitry is static,
the clock may be stopped and restarted for asynchronous memory operation if required.
Control Interfaces: Starting, Stopping, and Loading
COSMAC requires an external single-phase clock. Each machine cycle consists of eight clock pulses.
A 2-MHz clock frequency would yield a 4-microsecond machine cycle and result in an operating speed of
125,000 instructions per second.
During normal operation, the COSMAC CLEAR line must be held high. A momentary low on this line
places COSMAC in an IDLE state by forcing an IDLE instruction with P=O, R (0)=0000, and I E=1.
The COSMAC
LoAD"
line should also be held high during normal operation. Following CLEAR, a low
LOAD line permi1:s input bytes to be sequentially loaded into memory beginning at M (0000). Input bytes
can be supplied from a keyboard, tape reader, etc. This feature permits direct program loading without the
use of external ROM's or PROM's.
Fig. 43 illustrates one method of using the ~, CLOCK, and LOAD lines to control a COSMAC
system. All logic consists of standard 4000-series CMOS circuits. A free-running Pierce crystal oscillator
using a single 4007 chip provides a suitable gated clock. A high CLEAR on the control lead of the NAND
gate formed from the 4007 gates the oscillator output to the COSMAC CPU. When CLEAR is low, CLOCK
remains high. COSMAC design permits an asynchronous relationship between the free-running clock and
switch closures; a short first clock pulse will not affect COSMAC operation.
The two toggle switches control the operation of this system. When both switches are off, as shown in
Fig. 43, the CLEAR line is held low and the CLOCK line is held high. This CLEAR signal resets COSMAC
and can also be used to initialize I/O circuits.
If the LOAD switch is turned on, the CLEAR line will go high, the clock will be started, and the LOAD
line will be held low. COSMAC will remain in an IDLE state until a low occurs on the INTERRUPT, DMA-
iN,
or DMA-OUT line. Input circuits (not shown) can then activate DMA-IN to load bytes into memory.
The low
iJ)Aj)
line causes COSMAC to return to the IDLE state after each input byte is loaded.
Turning off the LOAD switch after a program has been loaded turns off the clock, holds the LOAD
line high, and puts the CLEAR line back to a low state. This sequence resets COSMAC once again, putting
it in an IDLE state.
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