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34 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ User Manual for the
Ten memory address bits are required to select lout of 1024 memory byte
location~high-order
byte (A.1) of a 16-bit COSMAC memory address appears on the memory
addres~s
MAO-7 first. The
two least-significant bits are strobed into the 2-bit address latch by timing pulse A (TPA). Fig. 42 shows the
timing.
~
I+-
T(NOTE
I)
MEMORY TIMING:
ADDRESS (MAO TO MA 7)
M READ
MWR (NOTE 2)
MEMORY OUTPUT
2'ZW/ZI)
V//~~/I1~
k0?
j
I
'VALID BYTE
-""""""'NOTE 3
~VALID
BYTE
!.-ALLOWABLE MEMORY ACCESS TIME
~
3.5T-ts
(ts=SETTLING TIME)
92CM-26472
NOTES:
1. MINIMUM T DETERMINED BY VDD--NO MAXIMUM T
2. MEMORY WRITE PULSE WIDTH (MWR);:::: 1.5 T
3. MEMORY OUTPUT "OFF" INDICATES HIGH-IMPEDANCE CONDITION.
4. SHADING INDICATES "DON'T CARE" OR INTERNAL DELAYS DEPENDING ON
VDD AND THE CLOCK SPEED.
Fig.
42 -
Memory read/write timing.
The low-order byte (A.O) of a 16-bit COSMAC memory address appears on the MAO-7 lines after the
high-order bits have been strobed into the address latch. Latching all eight A.1 bits would permit memory
expansion to 65,536 bytes. Chip select decoding would have to be added to the latch output for memory
expansion. The MAO-7 lines may also require buffer circuits to reduce the load on them to achieve high
speed.
The state of the MWR and MREAD lines determine whether a byte is to be read from or written into the
addressed memory location. COSMAC controls the destination of the memory output byte when it appears
on the data bus. It may be strobed into an internal COSMAC register or an external I/O register.
A high MREAD line forces a high-impedance state at the output of the memory. COSMAC or I/Ocir-
cuits can then place a byte to be stored in memory on the bus. A positive-going MWR pulse will cause the
data byte to be written into the addressed memory location.
When a data bit is true ("1 "), the corresponding bus line is low; when data is false ("0"), the corre-
sponding line is high. Eight bus pull-up resistors should be provided to place the bus in a known state when
it is not being driven.
Other standard RAM types are readily accommodated by the COSMACinterface lines. Access time
must be consistent with clock frequency; e.g., a 2-MHz clock will require a memory with a maximum access
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