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COSMAC Microprocessor
41
Fig. 47 illustrates the use of the INPUT instruction in conjunction with a flag line. Eight input switches
are first set to represent a desired input byte (l=low, O=high). Momentarily pressing the ENTER switch then
places a low on the EFl line. The program monitors the status of this line. When a low is detected, the
program branches to an INPUT instruction (1=6 and N3=1).
COSMAC
TPA
4069
u
EFI
n
"1"
,-----0
8 INPUT
-.L
~WITeHES
"SW -- BUS" eON
T
ROL
ION
H)
14------1Q
ENTER
S
14-4>----D
R~~~Lw:c---'
92CM - 264 79
Fig. 47 - Simple byte input logic.
Vee
2
4066
SCO in a low state and SCl in a high state indicate that an input/output byte transfer cycle is being
performed. Ouringthiscycle the data byte is stored in the memory location addressed by R(X). The 3-input
gate in Fig. 47 transfers the state of the eight input switches to the bus through eight 4066 transmission
gates. The EFl line is forced high at TPA to assure that only one byte is entered per ENTER switch depres·
sion. This logic is suitable only if the single set of eight switches is the only input device in the system.
If more than one input device is required, NO through N2 can be decoded to specify up to eight
different input devices. The N3 signal can be replaced by a decoded N=9 signal. This arrangement would
permit the byte to be entered when 1=6 and N=9 (a 69 instruction). Instructions 68, 6A, 68, 6C, 60, 6E,
and 6F could then designate other devices or channels to enter data.
The eight input switches might be replaced by the byte output of a paper-tape reader, keyboard, or other
type of input device. The ENTER switch would then be replaced by a strobing signal generated by the
input device. The program must sample the flag line and execute input byte transfer instructions at speeds
consistent with the input byte transfer rate. Output devices can also utilize flag lines to signal COSMAC
that an output byte transfer is required.
The preceding examples have illustrated the use of the four flag lines, the 4-bit N code, the two state
code lines, the two timing lines, and the data bus for simple I/O operations. These I/O interface lines can be
used to implement more sophisticated I/O systems. Fig. 48 shows one such system.
The N digit provided by the input/output instruction (on NO-3) is decoded to provide 16 separate
control signals. One of these signals (N=O in this example) strobes an output byte into an 8-bit I/O device
select register. The outputs of this register are decoded to provide selection signals for up to 256 individual
I/O devices.
A 60 instruction is executed to place an 8-bit device selection code in the I/O device select register. Subse-
quent execution of a 61 instruction will send an 8-bit control code to the selected device or channel. Control
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