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Memory and Control
Interface·
33
The reader will find that Appendices B, C, and 0 are helpful while reading this section. Note that all
signal lines except Memory Write (MWR) are made active by holding them low, e.g., when the memory is to
be read, MREAD goes low (consistent with T2L bus conventions).
Memory Interface and Timing
The use of the COSMAC memory interface lines is best described by a specific example. Fig. 41 shows
the attachment of a static 1024·byte RAM. The 1024-byte read-write memory comprises eight 1024-bit
T A6780 RAM chips. These static single-power-supply chips are easy to use.
ADDRESS
0-9
MEMORY
1024 SYTES
TA67S0
STATIC RAM
CH IPS
WE
I - - - - < X '
S- DATA
IN SITS
3-STATE
OUTPUTS
CS
/ 4 - - - - - - - ( X
DATA BUS
MAO-I
COS MAC
f i
MWR
VCC
S SUS
PULL UP
RESISTORS
122 K)
92CS-26574
Fig.
41 -
Attachment of a static 1024-bit Random-Access-Memory (RAM)
to the COSMAC microprocessor.
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