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COSMAC Microprocessor _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 27
SKIP
R(P)+1
SKP
When 1=3 and N=8, the byte following the "38" instruction is skipped.
BRANCH I F
D~OO
M(R(P)) -+ R(P).O IF D100, OR R(P)+1
BNZ
When 1=3 and N=A, a branch is performed only if the byte in D does not equal zero; If it does, the next
instruction in sequence is executed.
A
01
23
N
A
~
-
P
1
ADDRESS
M
X
2
I
3
01
21
F6
R(O)
-
-
01
22
3A
R(1)
01
23
-
IALul-
I
•
A
01
23
N
A
cb
I-
p
1
X
2
ADDRESS
M
I
3
01
21
F6
R(O)
-
-
01
22
3A
R(I)
01
97
-
IALU
I-
I
01
23
97
R(2)
00
37
OF =-
01
23
97
R(2)
00
37
DF=-
01
24
2C
R(3)
-
-
I
o 112
I
01
24
2C
R(3)
-
-
I
0
lId
~
97
,
Fig. 34 - Example of instruction 3A - BRANCH IF
DIDO.
BRANCH IF NO DF
M(R(P)) -+ R(P).O IF DF = 0, OR R(P)+l
BNF
When 1=3 and N=B, a branch occurs only if DF=O. Otherwise, the next instruction in sequence is fetched
and executed.
3C
BRANCH IF NO EF1
M(R(P)) -+ R(P).O IF EF1=0, OR R(P)+1
BN1
3D
BRANCH IF NO EF2
M(R(P)) -+ R(P).O IF EF2=0, OR R(P)+1
BN2
3E
BRANCH IF NO EF2
M(R(P)) -+ R(P).O IF EF3 = 0, OR R(P)+1
BN3
3F
BRANCH IF NO EF4
M(R(P)) -+ R(P).O IF EF4 = 0, OR R(P)+1
BN4
When 1=3 and N=C,D,E, or F, a branc occurs only when the corresponding external flag input (EF1 ,2,3,
or 4) is in its "0" state.
Because only the low-order byte of R(P). can be modified by a branch instruction, the range of memory
locations that can be branched to is limited. Since only the low-order 8 bits can be modified, branching is
limited to 2
8
or 256 bytes. Each 256-byte memory segment is called a page. Methods for branching to any
location in memory are described in the section on Machine Code Programming.
The special case of a branch instruction and its immediate byte occupying the last two bytes in a page is
treated as follows: If a branch takes place, R(P).1 is not changed - - the branch stays on the same page. If a
branch does not take place, execution continues at the first (Oth) byte of the next page. A branch in-
struction on the last byte of a page always leads into the next page, either by branch or by increment. In
other words, the address of the immediate byte determines the page to which a branch takes place.
Control
100
I
IDLE
WAIT FOR INTERRUPT/DMA-IN/DMA-.oUT
IDL
When 1=0 and N=O, the microprocessor repeats execute (S1) cycles until an interrupt, DMA-in, or DMA-
out is activated, at which time the IDLE instruction is terminated. During IDLE, the microprocessor
continues to put out the two timing pulses for I/O synchronization.
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