Intel S2600WF Technical Product Specification page 38

Intel® Server Board S2600WF Product Family Technical Product Specification
3.3.1.7 Execute Disable Bit
Execute Disable Bit functionality can help prevent certain classes of malicious buffer overflow attacks when
combined with a supporting operating system. This allows the processor to classify areas in memory by
where application code can execute and where it cannot. When malicious code attempts to insert code in the
buffer, the processor disables code execution, preventing damage and further propagation.
3.3.1.8 Intel® Trusted Execution Technology for servers (Intel® TXT)
Intel® TXT defines platform-level enhancements that provide the building blocks for creating trusted
platforms. The Intel TXT platform helps to provide the authenticity of the controlling environment such that
those wishing to rely on the platform can make an appropriate trust decision. The Intel TXT platform
determines the identity of the controlling environment by accurately measuring and verifying the controlling
software.
3.3.1.9 Intel® Advanced Vector Extensions 512 (Intel AVX-512)
The base of the 512-bit single instruction multiple data (SIMD) instruction extensions are referred to as Intel®
AVX-512 foundation instructions. They include extensions of the Intel® Advanced Vector Extensions (Intel®
AVX) family of SIMD instructions but are encoded using a new scheme with support for 512-bit vector
registers, up to 32 vector registers in 64-bit mode, and conditional processing using opmask registers.
3.3.1.10 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)
Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI) is a set of instructions implemented in
all processors in the Fifth Generation Intel® Core™ Processor Family. This feature adds AES instructions to
accelerate encryption and decryption operations used in the Advanced Encryption Standard. The Intel AES-
NI feature includes six additional SIMD instructions in the Intel® Streaming SIMD Extensions (Intel® SSE)
instruction set.
The BIOS is responsible in POST to detect whether the processor has the Intel AES-NI instructions available.
Some processors may be manufactured without Intel AES-NI instructions.
The Intel AES-NI instructions may be enabled or disabled by the BIOS. Intel AES-NI instructions are enabled
unless the BIOS has explicitly disabled them.
3.3.1.11 Intel® Intelligent Power Node Manager 4.0
The Intel® ME on the Intel® C620 series chipset supports Intel® Intelligent Power Node Manager technology.
The Intel ME/Intel® Node Manager (Intel® NM) combination is a power and thermal control capability on the
platform, which exposes external interfaces that allow IT (through external management software) to query
the Intel ME about platform power capability and consumption, thermal characteristics, and specify policy
directives (that is, set a platform power budget). Intel ME enforces these policy directives by controlling the
power consumption of underlying subsystems using available control mechanisms (such as processor P/T
states). The determination of the policy directive is done outside of Intel ME either by intelligent
management software or by the IT operator.
Below are the some of the applications of Intel Intelligent Power Node Manager technology:
Platform power monitoring and limiting – The Intel ME/Intel NM monitors platform power
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consumption and holds average power over duration. It can be queried to return actual power at any
given instance. The power limiting capability is to allow external management software to address
key IT issues by setting a power budget for each server.
Inlet air temperature monitoring – The Intel ME/Intel NM monitors server inlet air temperatures
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periodically. If there is an alert threshold in effect, then Intel ME/Intel NM issues an alert when the
inlet (room) temperature exceeds the specified value. The threshold value can be set by policy.
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