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Table 10–2 Flat panel connector: J5
Pin #
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
* Pulled low by 0 ohm resistor. Can be configured as an
active PCIRST* signal as a special order from factory.
Figure 10–2
The XE–700 SBC and a flat panel display
74
J5 – flat panel connector
Pin Name
Pin Name
FPCLK
Gnd
Gnd
FPDATA[12], R0
FPDATA[0], B0
FPDATA[13], R1
FPDATA[1], B1
FPDATA[14], R2
FPDATA[2], B2
nc
FPDATA[3], B3
nc
Gnd
FPDATA[15], R3
FPDATA[4], B4
FPDATA[16], R4
FPDATA[5], B5
FPDATA[17], R5
FPDATA[6], G0
Gnd
FPDATA[7], G1
TFTDE
Gnd
VCC3
FPDATA[8], G2
VCC3
FPDATA[9], G3
FPFRAME
FPDATA[10], G4
Gnd
FPDATA[11], G5
FPLINE
Gnd
VCC3
PCIRST*
VCC3
Gnd
Gnd
Gnd
Gnd
XE–700
Pin #
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
TFT Flat Panel Display
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